Apparatus and Method of Differential IQ Frequency Up-Conversion

ABSTRACT

A balanced transmitter up-converts I and Q baseband signals directly from baseband-to-RF. The up-conversion process is sufficiently linear that no IF processing is required, even in communications applications that have stringent requirements on spectral growth. In operation, the balanced modulator sub-harmonically samples the I and Q baseband signals in a balanced and differential manner, resulting in harmonically rich signal. The harmonically rich signal contains multiple harmonic images that repeat at multiples of the sampling frequency, where each harmonic contains the necessary information to reconstruct the I and Q baseband signals. The differential sampling is performed according to a first and second control signals that are phase shifted with respect to each other. In embodiments of the invention, the control signals have pulse widths (or apertures) that operate to improve energy transfer to a desired harmonic in the harmonically rich signal. A bandpass filter can then be utilized to select the desired harmonic of interest from the harmonically rich signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/231,244 filed Sep. 13, 2011, which is a continuation of U.S. patentapplication Ser. No. 12/662,190, filed on Apr. 5, 2010, now U.S. Pat.No. 8,036,304, which is a continuation of U.S. patent application Ser.No. 11/358,395, filed on Feb. 22, 2006, now U.S. Pat. No. 7,693,230,which claims the benefit of U.S. Provisional Patent Application No.60/654,866, filed on Feb. 22, 2005, and application Ser. No. 13/231,244is a continuation-in-part of U.S. application Ser. No. 11/015,653, filedon Dec. 20, 2004, now U.S. Pat. No. 7,773,688, which is a continuationof U.S. application Ser. No. 09/525,615, filed on Mar. 14, 2000, nowU.S. Pat. No. 6,853,690, which claims the benefit of the followingprovisional applications: U.S. Provisional Application No. 60/177,381,filed on Jan. 24, 2000; U.S. Provisional Application No. 60/171,502,filed Dec. 22, 1999; U.S. Provisional Application No. 60/177,705, filedon Jan. 24, 2000; U.S. Provisional Application No. 60/129,839, filed onApr. 16, 1999; U.S. Provisional Application No. 60/158,047, filed onOct. 7, 1999; U.S. Provisional Application No. 60/171,349, filed on Dec.21, 1999; U.S. Provisional Application No. 60/177,702, filed on Jan. 24,2000;U.S. Provisional Application No. 60/180,667, filed on Feb. 7, 2000;and U.S. Provisional Application No. 60/171,496, filed on Dec. 22, 1999;all of which are incorporated by reference herein in their entireties.

CROSS REFERENCE TO OTHER APPLICATIONS

The following applications of common assignee are related to the presentapplication, and are herein incorporated by reference in theirentireties:

“Method and System for Frequency Up-Conversion,” Ser. No. 09/176,154,filed Oct. 21, 1998, now U.S. Pat. No. 6,091,940;

“Method and System for Ensuring Reception of a Communications Signal,”Ser. No. 09/176,415, filed Oct. 21, 1998, now U.S. Pat. No. 6,051,555;

“Integrated Frequency Translation And Selectivity,” Ser. No. 09/175,966,filed Oct. 21, 1998, now U.S. Pat. No. 6,049,706;

“Universal Frequency Translation, and Applications of Same,” Ser. No.09/176,027, filed Oct. 21, 1998;

“Applications of Universal Frequency Translation,” filed Mar. 3, 1999,Ser. No. 09/261,129, filed Mar. 3, 1999, now U.S. Pat. No. 6,370,371;

“Matched Filter Characterization and Implementation of UniversalFrequency Translation Method and Apparatus,” Ser. No. 09/521,878, filedon Mar. 9, 1999;

“Spread Spectrum Applications of Universal Frequency Translation,” SerNo. 09/525,185, filed on Mar. 4, 2000, now U.S. Pat. No. 7,110,435; and

“DC Offset, Re-radiation, and I/Q Solutions Using Universal FrequencyTranslation Technology,” Ser No. 09/526,041, filed on Mar. 14, 2000, nowU.S. Pat. No. 6,879,817.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally related to frequency up-conversion ofa baseband signal, and applications of same. The invention is alsodirected to embodiments for frequency down-conversion, and totransceivers.

2. Related Art

Various communication components and systems exist for performingfrequency up-conversion and down-conversion of electromagnetic signals.

SUMMARY OF THE INVENTION

The present invention is related to up-converting a baseband signal, andapplications of same. Such applications include, but are not limited to,up-converting a spread spectrum signal directly from baseband to radiofrequency (RF) without utilizing

any intermediate frequency (IF) processing. The invention is alsorelated to frequency down-conversion and includes down-converting an RFsignal directly to baseband, or to an IF frequency.

In embodiments, the invention differentially samples a baseband signalaccording to first and second control signals, resulting in aharmonically rich signal. The harmonically rich signal contains multipleharmonic images that each contain the necessary amplitude, frequency,and/or phase information to reconstruct the baseband signal. Theharmonic images in the harmonically rich signal repeat at the harmonicsof the sampling frequency (1/Ts) that are associated with the first andsecond control signals. In other words, the sampling is performedsub-harmonically according to the control signals. Additionally, thecontrol signals include pulses that have an associated pulse width TAthat is established to improve energy transfer to a desired harmonicimage in the harmonically rich signal. The desired harmonic image canoptionally be selected using a bandpass filter for transmission over acommunications medium.

In operation, the invention converts the input baseband signal from a(single-ended) input into a differential baseband signal having firstand second components. The first differential component is substantiallysimilar to the input baseband signal, and the second differentialcomponent is an inverted version of the input baseband signal. The firstdifferential component is sampled according to the first control signal,resulting in a first harmonically rich signal. Likewise, the seconddifferential component is sampled according to the second controlsignal, resulting in a second harmonically rich signal. The first andsecond harmonically rich signals are combined to generate the outputharmonically rich signal.

The sampling modules that perform the differentially sampling can beconfigured in a series or shunt configuration. In the seriesconfiguration, the baseband input is received at one port of thesampling module, and is gated to a second port of the sampling module,to generate the harmonically rich signal at the second port of thesampling module. In the shunt configuration, the baseband input isreceived at one port of the sampling module and is periodically shuntedto ground at the second port of the sampling module, according to thecontrol signal. Therefore, in the shunt configuration, the harmonicallyrich signal is generated at the first port of the sampling module andcoexists with the baseband input signal at the first port.

The first control signal and second control signals that control thesampling process are phase shifted relative to one another. Inembodiments of the invention, the phase-shift is 180 degree in referenceto a master clock signal, although the invention includes other phaseshift values. Therefore, the sampling modules alternately sample thedifferential components of the baseband signal. Additionally asmentioned above, the first and second control signals include pulseshaving a pulse width TA that is established to improve energy transferto a desired harmonic in the harmonically rich signal during thesampling process. More specifically, the pulse width TA is anon-negligible fraction of a period associated with a desired harmonicof interest. In an embodiment, the pulse width TA is one-half of aperiod of the harmonic of interest. Additionally, in an embodiment, thefrequency of the pulses in both the first and second control signal area sub-harmonic frequency of the output signal.

In further embodiments, the invention minimizes DC offset voltagesbetween the sampling modules during the differential sampling. In theserial configuration, this is accomplished by distributing a referencevoltage to the input and output of the sampling modules. The result ofminimizing (or preventing) DC offset voltages is that carrier insertionis minimized in the harmonics of the harmonically rich signal. In manytransmit applications, carrier insertion is undesirable because theinformation to be transmitted is carried in the sidebands, and anyenergy at the carrier frequency is wasted. Alternatively, some transmitapplications require sufficient earlier insertion for coherentdemodulation of the transmitted signal at the receiver. In theseapplications, the invention can be configured to generate offsetvoltages between sampling modules, thereby causing carrier insertion inthe harmonics of the harmonically rich signal.

An advantage is that embodiments of the invention up-convert a basebandsignal directly from baseband-to-RF without any IF processing, whilestill meeting the spectral growth requirements of the most demandingcommunications standards. (Other embodiments may employ if processing.)For example, in an IQ configuration, the invention can up-convert a CDMAspread spectrum signal directly from baseband-to-RF, and still meet theCDMA IS-95 figure-of-merit and spectral growth requirements. In otherwords, the invention is sufficiently linear and efficient during theup-conversion process that no IF filtering or amplification is requiredto meet the IS-95 figure-of-merit and spectral growth requirements. As aresult, the entire IF chain in a conventional CDMA

transmitter configuration can be eliminated, including the expensive andhard to integrate SAW filter. Since the SAW filter is eliminated,substantial portions of a CDMA transmitter that incorporate theinvention can be integrated onto a single CMOS chip that uses a standardCMOS process, although the invention is not limited to this exampleapplication.

In embodiments, the invention includes a balanced IQ DifferentialModulator according to embodiments of the present invention. The IQmodulator receives a differential in-phase signal and differentialquadrature signal, and up-converts the differential in-phase andquadrature signals to generate an IQ output signal 7514 that is appliedacross a load. The IQ output signal includes a plurality of harmonicimages, where each harmonic image contains the baseband information inthe I baseband signal and the Q baseband signal. In other words, eachharmonic image in the IQ output signal contains the necessary amplitude,frequency, and phase information to reconstruct the I baseband signaland the Q baseband signal. In embodiments, the up-converted I and Qbaseband signal are combined using a wire- or connection, instead of asummer or combiner.

The IQ invention can also be implemented in single-ended configuration,and is not limited to differential configurations. The invention canalso be implemented in differential and single-ended receiverconfigurations. The invention can also be implemented in a differentialand single-ended transceiver configuration.

Further features and advantages of the invention, as well as thestructure and operation of various embodiments of the invention, aredescribed in detail below with reference to the accompanying drawings.The drawing in which an element first appears is typically indicated bythe leftmost character(s) and/or digit(s) in the corresponding referencenumber.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will be described with reference to theaccompanying drawings, wherein:

FIG. 1A is a block diagram of a universal frequency translation (UFT)module according to an embodiment of the invention;

FIG. 1B is a more detailed diagram of a universal frequency translation(UFT) module according to an embodiment of the invention;

FIG. 1C illustrates a UFT module used in a universal frequencydown-conversion (UFD) module according to an embodiment of theinvention;

FIG. 1D illustrates a UFT module used in a universal frequencyup-conversion (UFU) module according to an embodiment of the invention;

FIG. 2A is a block diagram of a universal frequency translation (UFT)module according to embodiments of the invention;

FIG. 2B is a block diagram of a universal frequency translation (UFT)module according to embodiments of the invention;

FIG. 3 is a block diagram of a universal frequency up-conversion (UFU)module according to an embodiment of the invention;

FIG. 4 is a more detailed diagram of a universal frequency up-conversion(UFU) module according to an embodiment of the invention;

FIG. 5 is a block diagram of a universal frequency up-conversion (UFU)module according to an alternative embodiment of the invention;

FIGS. 6A-61 illustrate example waveforms used to describe the operationof the UFU module;

FIG. 7 illustrates a UFT module used in a receiver according to anembodiment of the invention;

FIG. 8 illustrates a UFT module used in a transmitter according to anembodiment of the invention;

FIG. 9 illustrates an environment comprising a transmitter and areceiver, each of which may be implemented using a UFT module of theinvention;

FIG. 10 illustrates a transceiver according to an embodiment of theinvention;

FIG. 11 illustrates a transceiver according to an alternative embodimentof the invention;

FIG. 12 illustrates an environment comprising a transmitter and areceiver, each of which may be implemented using enhanced signalreception (ESR) components of the invention;

FIG. 13 illustrates a UFT module used in a unified down-conversion andfiltering (UDF) module according to an embodiment of the invention;

FIG. 14 illustrates an example receiver implemented using a UDF moduleaccording to an embodiment of the invention;

FIGS. 15A-15F illustrate example applications of the UDF moduleaccording to embodiments of the invention;

FIG. 16 illustrates an environment comprising a transmitter and areceiver, each of which may be implemented using enhanced signalreception (ESR) components of the invention, wherein the receiver may befurther implemented using one or more UFD modules of the invention;

FIG. 17 illustrates a unified down-converting and filtering (UDF) moduleaccording to an embodiment of the invention;

FIG. 18 is a table of example values at nodes in the UDF module of FIG.17;

FIG. 19 is a detailed diagram of an example UDF module according to anembodiment of the invention;

FIGS. 20A and 20A-1 are example aliasing modules according toembodiments of the invention;

FIGS. 20B-20F are example waveforms used to describe the operation ofthe aliasing modules of FIGS. 20A and 20A-1;

FIG. 21 illustrates an enhanced signal reception system according to anembodiment of the invention;

FIGS. 22A-22F are example waveforms used to describe the system of FIG.21;

FIG. 23A illustrates an example transmitter in an enhanced signalreception system according to an embodiment of the invention;

FIGS. 23B and 23C are example waveforms used to further describe theenhanced signal reception system according to an embodiment of theinvention;

FIG. 23D illustrates another example transmitter in an enhanced signalreception system according to an embodiment of the invention;

FIGS. 23E and 23F are example waveforms used to further describe theenhanced signal reception system according to an embodiment of theinvention;

FIG. 24A illustrates an example receiver in an enhanced signal receptionsystem according to an embodiment of the invention;

FIGS. 24B-24J are example waveforms used to further describe theenhanced signal reception system according to an embodiment of theinvention;

FIGS. 25A-B illustrate carrier insertion;

FIGS. 26A-C illustrate a balanced transmitter 2602 according to anembodiment of the present invention;

FIG. 26B-C illustrate example waveforms that are associated with thebalanced transmitter 2602 according to an embodiment of the presentinvention;

FIG. 26D illustrates example FET configurations of the balancedtransmitter 2602;

FIGS. 27A-i illustrate various example timing diagrams associated withthe transmitter 2602;

FIG. 27J illustrates an example frequency spectrum associated with themodulator 2604;

FIG. 28A illustrate a balanced modulator 2802 configured for carrierinsertion according to embodiments of the present invention;

FIG. 28B illustrates example signal diagrams associated with thebalanced transmitter 2802 according to embodiments of the invention;

FIG. 29 illustrates an I Q balanced transmitter 2920 according toembodiments of the present invention;

FIGS. 30A-C illustrate various example signal diagrams associated withthe balanced transmitter 2920 in FIG. 29;

FIG. 31A illustrates an I Q balanced transmitter 3108 according toembodiments of the invention;

FIG. 31B illustrates an I Q balanced modulator 3118 according toembodiments of the invention;

FIG. 32 illustrates an I Q balanced modulator 3202 configured forcarrier insertion according to embodiments of the invention;

FIG. 33 illustrates an I Q balanced modulator 3302 configured forcarrier insertion according to embodiments of the invention;

FIGS. 34A-B illustrate various input configurations for the balancedtransmitter 2920 according to embodiments of the present invention;

FIGS. 35A-B illustrate sidelobe requirements according to the IS-95 CDMAspecification;

FIG. 36 illustrates a conventional CDMA transmitter 3600;

FIG. 37A illustrates a CDMA transmitter 3700 according to embodiments ofthe present invention;

FIGS. 37B-E illustrate various example signal diagrams according toembodiments of the present invention;

FIG. 37F illustrates a CDMA transmitter 3720 according to embodiments ofthe present invention;

FIG. 38 illustrates a CDMA transmitter utilizing a CMOS chip accordingto embodiments of the present invention;

FIG. 39 illustrates an example test set 3900;

FIGS. 40-52Z illustrate various example test results from testing themodulator 2910 in the test set 3900;

FIGS. 53A-C illustrate a transmitter 5300 and associated signal diagramsaccording to embodiments of the present invention;

FIGS. 54A-B illustrate a transmitter 5400 and associated signal diagramsaccording to embodiments of the present invention;

FIG. 54C illustrates a transmitter 5430 according to embodiments of theinvention;

FIGS. 55A-D illustrates various implementation circuits for themodulator 2910 according to embodiments of the present invention, FIG.55B includes FIG. 55B1-B3, and FIG. 55C includes FIG. 55C1-55C3;

FIG. 56A illustrate a transmitter 5600 according to embodiments of thepresent invention;

FIGS. 56B-C illustrate various frequency spectrums that are associatedwith the transmitter 5600;

FIG. 56D illustrates a FET configuration for the modulator 5600;

FIG. 57 illustrates a IQ transmitter 5700 according to embodiments ofthe present invention;

FIGS. 58A-C illustrate various frequency spectrums that are associatedwith the IQ transmitter 5700;

FIG. 59 illustrates an IQ transmitter 5900 according to embodiments ofthe present invention;

FIG. 60 illustrates an IQ transmitter 6000 according to embodiments ofthe present invention;

FIG. 61 illustrates an IQ transmitter 6100 according to embodiments ofthe invention;

FIG. 62 illustrates a flowchart 6200 that is associated with thetransmitter 2602 in the FIG. 26A according to an embodiment of theinvention;

FIG. 63 illustrates a flowchart 6300 that further defines the flowchart6200 in the FIG. 62, and is associated with the transmitter 2602according to an embodiment of the invention;

FIG. 64 illustrates a flowchart 6400 that further defines the flowchart6200 in the FIG. 63 and is associated with the transmitter 6400according to an embodiment of the invention;

FIG. 65 illustrates the flowchart 6500 that is associated with thetransmitter 2920 in the FIG. 29 according to an embodiment of theinvention;

FIG. 66 illustrates a flowchart 6600 that is associated with thetransmitter 5700 according to an embodiment of the invention;

FIG. 67 illustrates a flowchart 6700 that is associated with the spreadspectrum transmitter 5300 in FIG. 53A according to an embodiment of theinvention;

FIG. 68A and FIG. 68B illustrate a flowchart 6800 that is associatedwith an IQ spread spectrum modulator 6100 in FIG. 61 according to anembodiment of the invention;

FIG. 69A and FIG. 69B illustrate a flowchart 6900 that is associatedwith an IQ spread spectrum transmitter 5300 in FIG. 54A according to anembodiment of the invention;

FIGS. 70A1 and 70A2 illustrate an IQ receiver having shunt UFT modulesaccording to embodiments of the invention;

FIG. 70B illustrates control signal generator embodiments for receiver7000 according to embodiments of the invention;

FIGS. 70C-D illustrate various control signal waveforms according toembodiments of the invention;

FIGS. 70E1 and 70E2 illustrates an example IQ modulation receiverembodiment according to embodiments of the invention;

FIGS. 70E-P illustrate example waveforms that are representative of theIQ receiver in FIGS. 70E1 and 70E2;

FIGS. 70Q-R illustrate single channel receiver embodiments according toembodiments of the invention;

FIG. 71 illustrates a transceiver 7100 according to embodiments of thepresent invention;

FIG. 72 illustrates a transceiver 7200 according to embodiments of thepresent invention;

FIG. 73 illustrates a flowchart 7300 that is associated with the CDMAtransmitter 3720 in FIG. 37 according to an embodiment of the invention;

FIG. 74A illustrates various pulse generators according to embodimentsof the invention;

FIGS. 74B-C illustrate various example signal diagrams associated withthe pulse generator in FIG. 74A, according to embodiments of theinvention; and

FIGS. 74D-E illustrate various additional pulse generators according toembodiments of the invention.

FIG. 75 illustrates a balanced IQ differential Modulator according toembodiments of the present invention.

FIG. 76A-B illustrate control signals and the IQ result for the IQdifferential modulator of FIG. 75

FIG. 77 a-g illustrate signal diagrams associated with the balanced IQdifferential modulator in FIG. 75.

FIG. 78 illustrates a flowchart that further describes the invention ofup-converting a baseband signal using a wire-or configuration.

FIG. 79 illustrates a single-ended version of the differentialup-converter in FIG. 75.

FIG. 80 illustrates an IQ differential receiver according to embodimentsof the Present invention.

FIG. 81 illustrates a flowchart that further describes the invention ofdown-converting a baseband signal using a wire-or device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1. Universal FrequencyTranslation

The present invention is related to frequency translation, andapplications of same. Such applications include, but are not limited to,frequency down-conversion, frequency up-conversion, enhanced signalreception, unified down-conversion and filtering, and combinations andapplications of same.

FIG. 1A illustrates a universal frequency translation (UFT) module 102according to embodiments of the invention. (The UFT module is alsosometimes called a universal frequency translator, or a universaltranslator.)

As indicated by the example of FIG. 1A, some embodiments of the UFTmodule 102 include three ports (nodes), designated in FIG. 1A as Port 1,Port 2, and Port 3. Other UFT embodiments include other than threeports.

Generally, the UFT module 102 (perhaps in combination with othercomponents) operates to generate an output signal from an input signal,where the frequency of the output signal differs from the frequency ofthe input signal. In other words, the UFT module 102 (and perhaps othercomponents) operates to generate the output signal from the input signalby translating the frequency (and perhaps other characteristics) of theinput signal to the frequency (and perhaps other characteristics) of theoutput signal.

An example embodiment of the UFT module 103 is generally illustrated inFIG. 1B. Generally, the UFT module 103 includes a switch 106 controlledby a control signal 108. The switch 106 is said to be a controlledswitch.

As noted above, some UFT embodiments include other than three ports. Forexample, and without limitation, FIG. 2 illustrates an example UFTmodule 202. The example UFT module 202 includes a diode 204 having twoports, designated as Port 1 and Port 2/3. This embodiment does notinclude a third port, as indicated by the dotted line around the “Port3” label. FIG. 2B illustrates a second example UFT module 208 having aFET 210 whose gate is controlled by the control signal.

The UFT module is a very powerful and flexible device. Its flexibilityis illustrated, in part, by the wide range of applications in which itcan be used. Its power is illustrated, in part, by the usefulness andperformance of such applications.

For example, a UFT module 115 can be used in a universal frequencydown-conversion (UFD) module 114, an example of which is shown in FIG.1C. In this

capacity, the UFT module 115 frequency down-converts an input signal toan output signal.

As another example, as shown in FIG. 1D, a UFT module 117 can be used ina universal frequency up-conversion (UFU) module 116. In this capacity,the UFT module 117 frequency up-converts an input signal to an outputsignal.

These and other applications of the UFT module are described below.Additional applications of the UFT module will be apparent to personsskilled in the relevant art(s) based on the teachings contained herein.In some applications, the UFT module is a required component. In otherapplications, the UFT module is an optional component.

2. Frequency Down-Conversion

The present invention is directed to systems and methods of universalfrequency down-conversion, and applications of same.

In particular, the following discussion describes down-converting usinga Universal Frequency Translation Module. The down-conversion of an EMsignal by aliasing the EM signal at an aliasing rate is fully describedin co-pending U.S. patent application entitled “Method and System forDown-Converting Electromagnetic Signals,” Ser. No. 09/176,022, filedOct. 21, 1998, the fall disclosure of which is incorporated herein byreference. A relevant portion of the above mentioned patent applicationis summarized below to describe down-converting an input signal toproduce a down-converted signal that exists at a lower frequency or abaseband signal.

FIG. 20A illustrates an aliasing module 2000 (one embodiment of a UFDmodule) for down-conversion using a universal frequency translation(UFT) module 2002, which down-converts an EM input signal 2004. Inparticular embodiments, aliasing module 2000 includes a switch 2008 anda capacitor 2010. The electronic alignment of the circuit components isflexible. That is, in one implementation, the switch 2008 is in serieswith input signal 2004 and capacitor 2010 is shunted to ground (althoughit may be other than ground in configurations such as differentialmode). In a second implementation (see FIG. 20A-1), the capacitor 2010is in series with the input signal 2004 and the switch 2008 is shuntedto ground (although it may be other than ground in configurations suchas differential mode). Aliasing module 2000 with UFT module 2002 can beeasily tailored to down-convert a wide variety of electromagneticsignals using aliasing frequencies that are well below the frequenciesof the EM input signal 2004.

In one implementation, aliasing module 2000 down-converts the inputsignal 2004 to an intermediate frequency (IF) signal. In anotherimplementation, the aliasing module 2000 down-converts the input signal2004 to a demodulated baseband signal. In yet another implementation,the input signal 2004 is a frequency modulated (FM) signal, and thealiasing module 2000 down-converts it to a non-FM signal, such as aphase modulated (PM) signal or an amplitude modulated (AM) signal. Eachof the above implementations is described below.

In an embodiment, the control signal 2006 includes a train of pulsesthat repeat at an aliasing rate that is equal to, or less than, twicethe frequency of the input signal 2004. In this embodiment, the controlsignal 2006 is referred to herein as an aliasing signal because it isbelow the Nyquist rate for the frequency of the input signal 2004.Preferably, the frequency of control signal 2006 is much less than theinput signal 2004.

A train of pulses 2018 as shown in FIG. 20D controls the switch 2008 toalias the input signal 2004 with the control signal 2006 to generate adown-converted output signal 2012. More specifically, in an embodiment,switch 2008 closes on a first edge of each pulse 2020 of FIG. 20D andopens on a second edge of each pulse. When the switch 2008 is closed,the input signal 2004 is coupled to the capacitor 2010, and charge istransferred from the input signal to the capacitor 2010. The chargestored during successive pulses forms down-converted output signal 2012.

Exemplary waveforms are shown in FIGS. 20B-20F.

FIG. 20B illustrates an analog amplitude modulated (AM) carrier signal2014 that is an example of input signal 2004. For illustrative purposes,in FIG. 20C, an analog AM carrier signal portion 2016 illustrates aportion of the analog AM carrier signal 2014 on an expanded time scale.The analog AM carrier signal portion 2016 illustrates the analog AMcarrier signal 2014 from time to to time ti.

FIG. 20D illustrates an exemplary aliasing signal 2018 that is anexample of control signal 2006. Aliasing signal 2018 is on approximatelythe same time scale as the analog AM carrier signal portion 2016. In theexample shown in FIG. 20D, the aliasing signal 2018 includes a train ofpulses 2020 having negligible apertures that tend towards zero (theinvention is not limited to this embodiment, as discussed below). Thepulse aperture may also be referred to as the pulse width as will beunderstood by those skilled in the art(s). The pulses 2020 repeat at analiasing rate, or pulse repetition rate of aliasing

signal 2018. The aliasing rate is determined as described below, andfurther described in co-pending U.S. patent application entitled “Methodand System for Down-converting Electromagnetic Signals,” Ser. No.09/176,022, filed on Oct. 21, 1998, now U.S. Pat. No. 6,061,551.

As noted above, the train of pulses 2020 (i.e., control signal 2006)control the switch 2008 to alias the analog AM carrier signal 2016(i.e., input signal 2004) at the aliasing rate of the aliasing signal2018. Specifically, in this embodiment, the switch 2008 closes on afirst edge of each pulse and opens on a second edge of each pulse. Whenthe switch 2008 is closed, input signal 2004 is coupled to the capacitor2010, and charge is transferred from the input signal 2004 to thecapacitor 2010. The charge transferred during a pulse is referred toherein as an under-sample. Exemplary under-samples 2022 formdown-converted signal portion 2024 (FIG. 20E) that corresponds to theanalog AM carrier signal portion 2016 (FIG. 20C) and the train of pulses2020 (FIG. 20D). The charge stored during successive under-samples of AMcarrier signal 2014 form the down-converted signal 2024 (FIG. 20E) thatis an example of down-converted output signal 2012 (FIG. 20A). In FIG.20F, a demodulated baseband signal 2026 represents the demodulatedbaseband signal 2024 after filtering on a compressed time scale. Asillustrated, down-converted signal 2026 has substantially the same“amplitude envelope” as AM carrier signal 2014. Therefore, FIGS. 20B-20Fillustrate down-conversion of AM carrier signal 2014.

The waveforms shown in FIGS. 20B-20F are discussed herein forillustrative purposes only, and are not limiting. Additional exemplarytime domain and frequency domain drawings, and exemplary methods andsystems of the invention relating thereto, are disclosed in co-pendingU.S. patent application entitled “Method and System for Down-convertingElectromagnetic Signals,” Ser. No. 09/176,022, filed on Oct. 21, 1998,now U.S. Pat. No. 6,061,551.

The aliasing rate of control signal 2006 determines whether the inputsignal 2004 is down-converted to an IF signal, down-converted to ademodulated baseband signal, or down-converted from an FM signal to a PMor an AM signal. Generally, relationships between the input signal 2004,the aliasing rate of the control signal 2006, and the down-convertedoutput signal 2012 are illustrated below:

(Freq. of input signal 2004)=n·(Freq. of control signal 2006)±(Freq. ofdown-converted output signal 2012)

For the examples contained herein, only the “+” condition will bediscussed. The value of n represents a harmonic or sub-harmonic of inputsignal 2004 (e.g., n=0.5, 1, 2, 3, . . . ).

When the aliasing rate of control signal 2006 is off-set from thefrequency of input signal 2004, or off-set from a harmonic orsub-harmonic thereof, input signal 2004 is down-converted to an IFsignal. This is because the under-sampling pulses occur at differentphases of subsequent cycles of input signal 2004. As a result, theunder-samples form a lower frequency oscillating pattern. If the inputsignal 2004 includes lower frequency changes, such as amplitude,frequency, phase, etc., or any combination thereof, the charge storedduring associated under-samples reflects the lower frequency changes,resulting in similar changes on the down-converted IF signal. Forexample, to down-convert a 901 MHZ input signal to a 1 MHZ IF signal,the frequency of the control signal 2006 would be calculated as follows:

(Freq_(input)−Freq_(1F))/n=Freq_(control)

(901 MHZ−1 MHZ)/n=900/n

For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006would be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225MHZ, etc.

Exemplary time domain and frequency domain drawings, illustrating downconversion of analog and digital AM, PM and FM signals to IF signals,and exemplary methods and systems thereof, are disclosed in co-pendingU.S. patent application entitled “Method and System for Down-convertingElectromagnetic Signals,” application Ser. No. 09/176,022, filed on Oct.21, 1998, now U.S. Pat. No. 6,061,551.

Alternatively, when the aliasing rate of the control signal 2006 issubstantially equal to the frequency of the input signal 2004, orsubstantially equal to a harmonic or sub-harmonic thereof, input signal2004 is directly down-converted to a demodulated baseband signal. Thisis because, without modulation, the under-sampling pulses occur at thesame point of subsequent cycles of the input signal 2004. As a result,the under-samples form a constant output baseband signal. If the inputsignal 2004 includes lower frequency changes, such as amplitude,frequency, phase, etc., or any combination thereof, the charge storedduring associated under-samples reflects the lower frequency changes,resulting in similar changes on the demodulated baseband signal Forexample, to

directly down-convert a 900 MHZ input signal to a demodulated basebandsignal (i.e., zero IF), the frequency of the control signal 2006 wouldbe calculated as follows:

(Freq_(input)−Freq_(1F))/n=Freq_(control)

(901 MHZ−0 MHZ)/n=900 MHZ/n

For n=0.5, 1, 2, 3, 4, etc., the frequency of the control signal 2006should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225MHZ, etc.

Exemplary time domain and frequency domain drawings, illustrating directdown-conversion of analog and digital AM and PM signals to demodulatedbaseband signals, and exemplary methods and systems thereof, aredisclosed in the co-pending U.S. patent application entitled “Method andSystem for Down-converting Electromagnetic Signals,” Ser. No.09/176,022, filed on Oct. 21, 1998, now U.S. Pat. No. 6,061,551.

Alternatively, to down-convert an input FM signal to a non-FM signal, afrequency within the FM bandwidth must be down-converted to baseband(i.e., zero IF). As an example, to down-convert a frequency shift keying(FSK) signal (a sub-set of FM) to a phase shift keying (PSK) signal (asubset of PM), the mid-point between a lower frequency F₁ and an upperfrequency F₂ (that is, [(F₁+F₂)÷2]) of the FSK signal is down-convertedto zero IF. For example, to down-convert an FSK signal having F₁ equalto 899 MHZ and F₂ equal to 901 MHZ, to a PSK signal, the aliasing rateof the control signal 2006 would be calculated as follows:

$\begin{matrix}{{{Frequency}\mspace{14mu} {of}\mspace{14mu} {the}\mspace{14mu} {input}} = {\left( {F_{1} + F_{2}} \right) \div 2}} \\{= {\left( {{899\mspace{14mu} {MHZ}} + {901\mspace{14mu} {MHZ}}} \right) \div 2}} \\{= {900\mspace{14mu} {MHZ}}}\end{matrix}$

Frequency of the down-converted signal=0 (i.e., baseband)

(Freq_(input)−Freq_(1F))/n=Freq_(control)

(901 MHZ−0 MHZ)/n=900 MHZ/n

For n 0.5, 1, 2, 3, etc., the frequency of the control signal 2006should be substantially equal to 1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225MHZ, etc. The frequency of the down-converted PSK signal issubstantially equal to one half the difference between the lowerfrequency F₁ and the upper frequency F₂.

As another example, to down-convert a FSK signal to an amplitude shiftkeying (ASK) signal (a subset of AM), either the lower frequency F₁ orthe upper frequency F₂ of the FSK signal is down-converted to zero IF.For example, to down-convert an FSK

signal having F₁ equal to 900 MHZ and F₂ equal to 901 MHZ, to an ASKsignal, the aliasing rate of the control signal 2006 should besubstantially equal to:

(900 MHZ−0 MHZ)/n=900 MHZ/n, or

(901 MHZ−0 MHZ)/n=901 MHZ/n.

For the former case of 900 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., thefrequency of the control signal 2006 should be substantially equal to1.8 GHz, 900 MHZ, 450 MHZ, 300 MHZ, 225 MHZ, etc. For the latter case of901 MHZ/n, and for n=0.5, 1, 2, 3, 4, etc., the frequency of the controlsignal 2006 should be substantially equal to 1.802 GHz, 901 MHZ, 450.5MHZ, 300.333 MHZ, 225.25 MHZ, etc. The frequency of the down-convertedAM signal is substantially equal to the difference between the lowerfrequency F₁ and the upper frequency F₂ (i.e., 1 MHZ).

Exemplary time domain and frequency domain drawings, illustratingdown-conversion of FM signals to non-FM signals, and exemplary methodsand systems thereof, are disclosed in the co-pending U.S. patentapplication entitled “Method and System for Down-convertingElectromagnetic Signals,” Ser. No. 09/176,022, filed on Oct. 21, 1998,now U.S. Pat. No. 6,061,551.

In an embodiment, the pulses of the control signal 2006 have negligibleapertures that tend towards zero. This makes the UFT module 2002 a highinput impedance device. This configuration is useful for situationswhere minimal disturbance of the input signal may be desired.

In another embodiment, the pulses of the control signal 2006 havenon-negligible apertures that tend away from zero. This makes the UFTmodule 2002 a lower input impedance device. This allows the lower inputimpedance of the UFT module 2002 to be substantially matched with asource impedance of the input signal 2004. This also improves the energytransfer from the input signal 2004 to the down-converted output signal2012, and hence the efficiency and signal to noise (s/n) ratio of UFTmodule 2002.

Exemplary systems and methods for generating and optimizing the controlsignal 2006, and for otherwise improving energy transfer and s/n ratio,are disclosed in the co-pending U.S. patent application entitled “Methodand System for Down-converting Electromagnetic Signals,” Ser. No.09/176,022, filed on Oct. 21, 1998, now U.S. Pat. No. 6,061,551.

3. Frequency Up-Conversion Using Universal Frequency Translation

The present invention is directed to systems and methods of frequencyup-conversion, and applications of same.

An example frequency up-conversion system 300 is illustrated in FIG. 3.The frequency up-conversion system 300 is now described.

An input signal 302 (designated as “Control Signal” in FIG. 3) isaccepted by a switch module 304. For purposes of example only, assumethat the input signal 302 is a FM input signal 606, an example of whichis shown in FIG. 6C. FM input signal 606 may have been generated bymodulating information signal 602 onto oscillating signal 604 (FIGS. 6Aand 6B). It should be understood that the invention is not limited tothis embodiment. The information signal 602 can be analog, digital, orany combination thereof, and any modulation scheme can be used.

The output of switch module 304 is a harmonically rich signal 306, shownfor example in FIG. 6D as a harmonically rich signal 608. Theharmonically rich signal 608 has a continuous and periodic waveform.

FIG. 6E is an expanded view of two sections of harmonically rich signal608, section 610 and section 612. The harmonically rich signal 608 maybe a rectangular wave, such as a square wave or a pulse (although, theinvention is not limited to this embodiment). For ease of discussion,the term “rectangular waveform” is used to refer to waveforms that aresubstantially rectangular. In a similar manner, the term “square wave”refers to those waveforms that are substantially square and it is notthe intent of the present invention that a perfect square wave begenerated or needed.

Harmonically rich signal 608 is comprised of a plurality of sinusoidalwaves whose frequencies are integer multiples of the fundamentalfrequency of the waveform of the harmonically rich signal 608. Thesesinusoidal waves are referred to as the harmonics of the underlyingwaveform, and the fundamental frequency is referred to as the firstharmonic. FIG. 6F and FIG. 6G show separately the sinusoidal componentsmaking up the first, third, and fifth harmonics of section 610 andsection 612. (Note that in theory there may be an infinite number ofharmonics; in this example, because harmonically rich signal 608 isshown as a square wave, there are only odd harmonics). Three harmonicsare shown simultaneously (but not summed) in FIG. 6H.

The relative amplitudes of the harmonics are generally a function of therelative widths of the pulses of harmonically rich signal 306 and theperiod of the fundamental

frequency, and can be determined by doing a Fourier analysis ofharmonically rich signal 306. According to an embodiment of theinvention, the input signal 606 may be shaped to ensure that theamplitude of the desired harmonic is sufficient for its intended use(e.g., transmission).

A filter 308 filters out any undesired frequencies (harmonics), andoutputs an electromagnetic (EM) signal at the desired harmonic frequencyor frequencies as an output signal 310, shown for example as a filteredoutput signal 614 in FIG. 61.

FIG. 4 illustrates an example universal frequency up-conversion (UFU)module 401. The UFUU module 401 includes an example switch module 304,which comprises a bias signal 402, a resistor or impedance 404, auniversal frequency translator (UFT) 450, and a ground 408. The UFT 450includes a switch 406. The input signal 302 (designated as “ControlSignal” in FIG. 4) controls the switch 406 in the UFT 450, and causes itto close and open. Harmonically rich signal 306 is generated at a node405 located between the resistor or impedance 404 and the switch 406.

Also in FIG. 4, it can be seen that an example filter 308 is comprisedof a capacitor 410 and an inductor 412 shunted to a ground 414. Thefilter is designed to filter out the undesired harmonics of harmonicallyrich signal 306.

The invention is not limited to the UFU embodiment shown in FIG. 4.

For example, in an alternate embodiment shown in FIG. 5, an unshapedinput signal 501 is routed to a pulse shaping module 502. The pulseshaping module 502 modifies the unshaped input signal 501 to generate a(modified) input signal 302 (designated as the “Control Signal” in FIG.5). The input signal 302 is routed to the switch module 304, whichoperates in the manner described above. Also, the filter 308 of FIG. 5operates in the manner described above.

The purpose of the pulse shaping module. 502 is to define the pulsewidth of the input signal 302. Recall that the input signal 302 controlsthe opening and closing of the switch 406 in switch module 304. Duringsuch operation, the pulse width of the input signal 302 establishes thepulse width of the harmonically rich signal 306. As stated above, therelative amplitudes of the harmonics of the harmonically rich signal 306are a function of at least the pulse width of the harmonically richsignal 306. As such, the pulse width of the input signal 302 contributesto setting the relative amplitudes of the harmonics of harmonically richsignal 306.

Further details of up-conversion as described in this section arepresented in pending U.S. application “Method and System for FrequencyUp-Conversion,” Ser. No. 09/176,154, filed Oct. 21, 1998, incorporatedherein by reference in its entirety.

4. Enhanced Signal Reception

The present invention is directed to systems and methods of enhancedsignal reception (ESR), and applications of same.

Referring to FIG. 21, transmitter 2104 accepts a modulating basebandsignal 2102 and generates (transmitted) redundant spectrums 2106 a-n,which are sent over communications medium 2108. Receiver 2112 recovers ademodulated baseband signal 2114 from (received) redundant spectrums2110 a-n. Demodulated baseband signal 2114 is representative of themodulating baseband signal 2102, where the level of similarity betweenthe modulating baseband signal 2114 and the modulating baseband signal2102 is application dependent.

Modulating baseband signal 2102 is preferably any information signaldesired for transmission and/or reception. An example modulatingbaseband signal 2202 is illustrated in FIG. 22A, and has an associatedmodulating baseband spectrum 2204 and image spectrum 2203 that areillustrated in FIG. 22B. Modulating baseband signal 2202 is illustratedas an analog signal in FIG. 22 a, but could also be a digital signal, orcombination thereof. Modulating baseband signal 2202 could be a voltage(or current) characterization of any number of real world occurrences,including for example and without limitation, the voltage (or current)representation for a voice signal.

Each transmitted redundant spectrum 2106 a-n contains the necessaryinformation to substantially reconstruct the modulating baseband signal2102. In other words, each redundant spectrum 2106 a-n contains thenecessary amplitude, phase, and frequency information to reconstruct themodulating baseband signal 2102.

FIG. 22C illustrates example transmitted redundant spectrums 2206 b-d.Transmitted redundant spectrums 2206 b-d are illustrated to containthree redundant spectrums for illustration purposes only. Any number ofredundant spectrums could be generated and transmitted as will beexplained in following discussions.

Transmitted redundant spectrums 2206 b-d are centered at f₁, with afrequency spacing f₂ between adjacent spectrums. Frequencies f₁ and f₂are dynamically adjustable in real-time as will be shown below. FIG. 22Dillustrates an alternate embodiment, where

redundant spectrums 2208 c,d are centered on unmodulated oscillatingsignal 2209 at f₁ (Hz). Oscillating signal 2209 may be suppressed ifdesired using, for example, phasing techniques or filtering techniques.Transmitted redundant spectrums are preferably above basebandfrequencies as is represented by break 2205 in the frequency axis ofFIGS. 22C and 22D.

Received redundant spectrums 2110 a-n are substantially similar totransmitted redundant spectrums 2106 a-n, except for the changesintroduced by the communications medium 2108. Such changes can includebut are not limited to signal attenuation, and signal interference. FIG.22E illustrates example received redundant spectrums 2210 b-d. Receivedredundant spectrums 2210 b-d are substantially similar to transmittedredundant spectrums 2206 b-d, except that redundant spectrum 2210 cincludes an undesired jamming signal spectrum 2211 in order toillustrate some advantages of the present invention. Jamming signalspectrum 2211 is a frequency spectrum associated with a jamming signal.For purposes of this invention, a “jamming signal” refers to anyunwanted signal, regardless of origin, that may interfere with theproper reception and reconstruction of an intended signal. Furthermore,the jamming signal is not limited to tones as depicted by spectrum 2211,and can have any spectral shape, as will be understood by those skilledin the art(s).

As stated above, demodulated baseband signal 2114 is extracted from oneor more of received redundant spectrums 2210 b-d. FIG. 22F illustratesexample demodulated baseband signal 2212 that is, in this example,substantially similar to modulating baseband signal 2202 (FIG. 22A);where in practice, the degree of similarity is application dependent.

An advantage of the present invention should now be apparent. Therecovery of modulating baseband signal 2202 can be accomplished byreceiver 2112 in spite of the fact that high strength jamming signal(s)(e.g. jamming signal spectrum 2211) exist on the communications medium.The intended baseband signal can be recovered because multiple redundantspectrums are transmitted, where each redundant spectrum carries thenecessary information to reconstruct the baseband signal. At thedestination, the redundant spectrums are isolated from each other sothat the baseband signal can be recovered even if one or more of theredundant spectrums are corrupted by a jamming signal.

Transmitter 2104 will now be explored in greater detail. FIG. 23Aillustrates transmitter 2301, which is one embodiment of transmitter2104 that generates redundant spectrums configured similar to redundantspectrums 2206 b-d. Transmitter 2301 includes generator 2303, optionalspectrum processing module 2304, and optional medium interface module2320. Generator 2303 includes: first oscillator 2302, second oscillator2309, first stage modulator 2306, and second stage modulator 2310.

Transmitter 2301 operates as follows. First oscillator 2302 and secondoscillator 2309 generate a first oscillating signal 2305 and secondoscillating signal 2312, respectively. First stage modulator 2306modulates first oscillating signal 2305 with modulating baseband signal2202, resulting in modulated signal 2308. First stage modulator 2306 mayimplement any type of modulation including but not limited to: amplitudemodulation, frequency modulation, phase modulation, combinationsthereof, or any other type of modulation. Second stage modulator 2310modulates modulated signal 2308 with second oscillating signal 2312,resulting in multiple redundant spectrums 2206 a-n shown in FIG. 23B.Second stage modulator 2310 is preferably a phase modulator, or afrequency modulator, although other types of modulation may beimplemented including but not limited to amplitude modulation. Eachredundant spectrum 2206 a-n contains the necessary amplitude, phase, andfrequency information to substantially reconstruct the modulatingbaseband signal 2202.

Redundant spectrums 2206 a-n are substantially centered around f₁, whichis the characteristic frequency of first oscillating signal 2305. Also,each redundant spectrum 2206 a-n (except for 2206 c) is offset from f₁by approximately a multiple of f₂ (Hz), where f₂ is the frequency of thesecond oscillating signal 2312. Thus, each redundant spectrum 2206 a-nis offset from an adjacent redundant spectrum by f₂ (Hz). This allowsthe spacing between adjacent redundant spectrums to be adjusted (ortuned) by changing f₂ that is associated with second oscillator 2309.Adjusting the spacing between adjacent redundant spectrums allows fordynamic real-time tuning of the bandwidth occupied by redundantspectrums 2206 a-n.

In one embodiment, the number of redundant spectrums 2206 a-n generatedby transmitter 2301 is arbitrary and may be unlimited as indicated bythe “a-n” designation for redundant spectrums 2206 a-n. However, atypical communications medium will have a physical and/or administrativelimitations (i.e. FCC regulations) that restrict the number

of redundant spectrums that can be practically transmitted over thecommunications medium. Also, there may be other reasons to limit thenumber of redundant spectrums transmitted. Therefore, preferably, thetransmitter 2301 will include an optional spectrum processing module2304 to process the redundant spectrums 2206 a-n prior to transmissionover communications medium 2108.

In one embodiment, spectrum processing module 2304 includes a filterwith a passband 2207 (FIG. 23C) to select redundant spectrums 2206 b-dfor transmission. This will substantially limit the frequency bandwidthoccupied by the redundant spectrums to the passband 2207. In oneembodiment, spectrum processing module 2304 also up-converts redundantspectrums and/or amplifies redundant spectrums prior to transmissionover the communications medium 2108. Finally, medium interface module2320 transmits redundant spectrums over the communications medium 2108.In one embodiment, communications medium 2108 is an over-the-air linkand medium interface module 2320 is an antenna. Other embodiments forcommunications medium 2108 and medium interface module 2320 will beunderstood based on the teachings contained herein.

FIG. 23D illustrates transmitter 2321, which is one embodiment oftransmitter 2104 that generates redundant spectrums configured similarto redundant spectrums 2208 c-d and unmodulated spectrum 2209.Transmitter 2321 includes generator 2311, spectrum processing module2304, and (optional) medium interface module 2320. Generator 2311includes: first oscillator 2302, second oscillator 2309, first stagemodulator 2306, and second stage modulator 2310.

As shown in FIG. 23D, many of the components in transmitter 2321 aresimilar to those in transmitter 2301. However, in this embodiment,modulating baseband signal 2202 modulates second oscillating signal2312. Transmitter 2321 operates as follows. First stage modulator 2306modulates second oscillating signal 2312 with modulating baseband signal2202, resulting in modulated signal 2322. As described earlier, firststage modulator 2306 can effect any type of modulation including but notlimited to: amplitude modulation frequency modulation, combinationsthereof, or any other type of modulation. Second stage modulator 2310modulates first oscillating signal 2304 with modulated signal 2322,resulting in redundant spectrums 2208 a-n, as shown in FIG. 23E. Second

stage modulator 2310 is preferably a phase or frequency modulator,although other modulators could used including but not limited to anamplitude modulator.

Redundant spectrums 2208 a-n are centered on unmodulated spectrum 2209(at f₁ Hz), and adjacent spectrums are separated by f₂ Hz. The number ofredundant spectrums 2208 a-n generated by generator 2311 is arbitraryand unlimited, similar to spectrums 2206 a-n discussed above. Therefore,optional spectrum processing module 2304 may also include a filter withpassband 2325 to select, for example, spectrums 2208 c,d fortransmission over communications medium 2108. In addition, optionalspectrum processing module 2304 may also include a filter (such as abandstop filter) to attenuate unmodulated spectrum 2209. Alternatively,unmodulated spectrum 2209 may be attenuated by using phasing techniquesduring redundant spectrum generation. Finally, (optional) mediuminterface module 2320 transmits redundant spectrums 2208 c,d overcommunications medium 2108.

Receiver 2112 will now be explored in greater detail to illustraterecovery of a demodulated baseband signal from received redundantspectrums. FIG. 24A illustrates receiver 2430, which is one embodimentof receiver 2112. Receiver 2430 includes optional medium interfacemodule 2402, down-converter 2404, spectrum isolation module 2408, anddata extraction module 2414. Spectrum isolation module 2408 includesfilters 2410 a-c. Data extraction module 2414 includes demodulators 2416a-c, error check modules 2420 a-c, and arbitration module 2424. Receiver2430 will be discussed in relation to the signal diagrams in FIGS.24B-24J.

In one embodiment, optional medium interface module 2402 receivesredundant spectrums 2210 b-d (FIG. 22E, and FIG. 24B). Each redundantspectrum 2210 b-d includes the necessary amplitude, phase, and frequencyinformation to substantially reconstruct the modulating baseband signalused to generated the redundant spectrums. However, in the presentexample, spectrum 2210 c also contains jamming signal 2211, which mayinterfere with the recovery of a baseband signal from spectrum 2210 c.Down-converter 2404 down-converts received redundant spectrums 2210 b-dto lower intermediate frequencies, resulting in redundant spectrums 2406a-c (FIG. 24C). Jamming signal 2211 is also down-converted to jammingsignal 2407, as it is contained within redundant spectrum 2406 b.Spectrum isolation module 2408 includes filters 2410 a-c that isolateredundant spectrums 2406 a-c from each other (FIGS. 24D-24F,respectively).

Demodulators 2416 a-c independently demodulate spectrums 2406 a-c,resulting in demodulated baseband signals 2418 a-c, respectively (FIGS.24G-24I). Error check modules 2420 a-c analyze demodulate basebandsignal 2418 a-c to detect any errors. In one embodiment, each errorcheck module 2420 a-c sets an error flag 2422 a-c whenever an error isdetected in a demodulated baseband signal. Arbitration module 2424accepts the demodulated baseband signals and associated error flags, andselects a substantially error-free demodulated baseband signal (FIG.24J). In one embodiment, the substantially error-free demodulatedbaseband signal will be substantially similar to the modulating basebandsignal used to generate the received redundant spectrums, where thedegree of similarity is application dependent.

Referring to FIGS. 24G-I, arbitration module 2424 will select eitherdemodulated baseband signal 2418 a or 2418 c, because error check module2420 b will set the error flag 2422 b that is associated withdemodulated baseband signal 2418 b.

The error detection schemes implemented by the error detection modulesinclude but are not limited to: cyclic redundancy check (CRC) and paritycheck for digital signals, and various error detections schemes foranalog signal.

Further details of enhanced signal reception as described in thissection are presented in pending U.S. application “Method and System forEnsuring Reception of a Communications Signal,” Ser. No. 09/176,415,filed Oct. 21, 1998, incorporated herein by reference in its entirety.

5. Unified Down-Conversion and Filtering

The present invention is directed to systems and methods of unifieddown-conversion and filtering (UDF), and applications of same.

In particular, the present invention includes a unified down-convertingand filtering (UDF) module that performs frequency selectivity andfrequency translation in a unified (i.e., integrated) manner. Byoperating in this manner, the invention achieves high frequencyselectivity prior to frequency translation (the invention is not limitedto this embodiment). The invention achieves high frequency selectivityat substantially any frequency, including but not limited to RF (radiofrequency) and greater frequencies. It should be understood that theinvention is not limited to this example of RF and greater frequencies.The invention is intended, adapted, and capable of working with lowerthan radio frequencies.

FIG. 17 is a conceptual block diagram of a UDF module 1702 according toan embodiment of the present invention. The UDF module 7.702 performs atleast frequency translation and frequency selectivity.

The effect achieved by the UDF module 1702 is to perform the frequencyselectivity operation prior to the performance of the frequencytranslation operation. Thus, the UDF module 1702 effectively performsinput filtering.

According to embodiments of the present invention, such input filteringinvolves a relatively narrow bandwidth. For example, such inputfiltering may represent channel select filtering, where the filterbandwidth may be, for example, 50 KHz to 150 KHz. It should beunderstood, however, that the invention is not limited to thesefrequencies. The invention is intended, adapted, and capable ofachieving filter bandwidths of less than and greater than these values.

In embodiments of the invention, input signals 1704 received by the UDFmodule 1702 are at radio frequencies. The UDF module 1702 effectivelyoperates to input filter these RF input signals 1704. Specifically, inthese embodiments, the UDF module 1702 effectively performs input,channel select filtering of the RF input signal 1704. Accordingly, theinvention achieves high selectivity at high frequencies.

The UDF module 1702 effectively performs various types of filtering,including but not limited to bandpass filtering, low pass filtering,high pass filtering, notch filtering, all pass filtering, band stopfiltering, etc., and combinations thereof.

Conceptually, the UDF module 1702 includes a frequency translator 1708.The frequency translator 1708 conceptually represents that portion ofthe UDF module 1702 that performs frequency translation (downconversion).

The UDF module 1702 also conceptually includes an apparent input filter1706 (also sometimes called an input filtering emulator). Conceptually,the apparent input filter 1706 represents that portion of the UDF module1702 that performs input filtering.

In practice, the input filtering operation performed by the UDF module1702 is integrated with the frequency translation operation. The inputfiltering operation can be viewed as being performed concurrently withthe frequency translation operation. This is a reason why the inputfilter 1706 is herein referred to as an “apparent” input filter 1706.

The UDF module 1702 of the present invention includes a number ofadvantages. For example, high selectivity at high frequencies isrealizable using the UDF module

1702. This feature of the invention is evident by the high Q factorsthat are attainable. For example, and without limitation, the UDF module1702 can be designed with a filter center frequency fc on the order of900 MHZ, and a filter bandwidth on the order of 50 KHz. This representsa Q of 18,000 (Q is equal to the center frequency divided by thebandwidth).

It should be understood that the invention is not limited to filterswith high Q factors. The filters contemplated by the present inventionmay have lesser or greater Qs, depending on the application, design,and/or implementation. Also, the scope of the invention includes filterswhere Q factor as discussed herein is not applicable.

The invention exhibits additional advantages. For example, the filteringcenter frequency f_(C) of the UDF module 1702 can be electricallyadjusted, either statically or dynamically.

Also, the UDF module 1702 can be designed to amplify input signals.

Further, the UDF module 1702 can be implemented without large resistors,capacitors, or inductors. Also, the UDF module 1702 does not requirethat tight tolerances be maintained on the values of its individualcomponents, i.e., its resistors, capacitors, inductors, etc. As aresult, the architecture of the UDF module 1702 is friendly tointegrated circuit design techniques and processes.

The features and advantages exhibited by the UDF module 1702 areachieved at least in part by adopting a new technological paradigm withrespect to frequency selectivity and translation. Specifically,according to the present invention, the UDF module 1702 performs thefrequency selectivity operation and the frequency translation operationas a single, unified (integrated) operation. According to the invention,operations relating to frequency translation also contribute to theperformance of frequency selectivity, and vice versa.

According to embodiments of the present invention, the UDF modulegenerates an output signal from an input signal using samples/instancesof the input signal and samples/instances of the output signal.

More particularly, first, the input signal is under-sampled. This inputsample includes information (such as amplitude, phase, etc.)representative of the input signal existing at the time the sample wastaken.

As described further below, the effect of repetitively performing thisstep is to translate the frequency (that is, down-convert) of the inputsignal to a desired lower frequency, such as an intermediate frequency(IF) or baseband.

Next, the input sample is held (that is, delayed).

Then, one or more delayed input samples (some of which may have beenscaled) are combined with one or more delayed instances of the outputsignal (some of which may have been scaled) to generate a currentinstance of the output signal.

Thus, according to a preferred embodiment of the invention, the outputsignal is generated from prior samples/instances of the input signaland/or the output signal. (It is noted that, in some embodiments of theinvention, current samples/instances of the input signal and/or theoutput signal may be used to generate current instances of the outputsignal). By operating in this manner, the UDF module preferably performsinput filtering and frequency down-conversion in a unified manner.

FIG. 19 illustrates an example implementation of the unifieddown-converting and filtering (UDF) module 1922. The UDF module 1922performs the frequency translation operation and the frequencyselectivity operation in an integrated, unified manner as describedabove, and as further described below.

In the example of FIG. 19, the frequency selectivity operation performedby the UDF module 1922 comprises a band-pass filtering operationaccording to EQ. 1, below, which is an example representation of aband-pass filtering transfer function.

VO=α ₁ z ⁻¹ VI−β ₁ z ⁻¹ VO−β ₀ z ⁻² VO  EQ. 1

It should be noted, however, that the invention is not limited toband-pass filtering. Instead, the invention effectively performs varioustypes of filtering, including but not limited to bandpass filtering, lowpass filtering, high pass filtering, notch filtering, all passfiltering, band stop filtering, etc., and combinations thereof. As willbe appreciated, there are many representations of any given filter type.The invention is applicable to these filter representations. Thus, EQ. 1is referred to herein for illustrative purposes only, and is notlimiting.

The UDF module 1922 includes a down-convert and delay module 1924, firstand second delay modules 1928 and 1930, first and second scaling modules1932 and 1934, an output sample and hold module 1936, and an (optional)output smoothing module 1938. Other embodiments of the UDF module willhave these components in different

configurations, and/or a subset of these components, and/or additionalcomponents. For example, and without limitation, in the configurationshown in FIG. 19, the output smoothing module 1938 is optional.

As further described below, in the example of FIG. 19, the down-convertand delay module 1924 and the first and second delay modules 1928 and1930 include switches that are controlled by a clock having two phases,φ₁ and φ₂. φ₁ and φ₂ preferably have the same frequency, and arenon-overlapping (alternatively, a plurality such as two clock signalshaving these characteristics could be used). As used herein, the term“non-overlapping” is defined as two or more signals where only one ofthe signals is active at any given time. In some embodiments, signalsare “active” when they are high. In other embodiments, signals areactive when they are low.

Preferably, each of these switches closes on a rising edge of φ₁ or φ₂,and opens on the next corresponding falling edge of φ₁ or φ₂. However,the invention is not limited to this example. As will be apparent topersons skilled in the relevant art(s), other clock conventions can beused to control the switches.

In the example of FIG. 19, it is assumed that a₁ is equal to one. Thus,the output of the down-convert and delay module 1924 is not scaled. Asevident from the embodiments described above, however, the invention isnot limited to this example.

The example UDF module 1922 has a filter center frequency of 900.2 MHZand a filter bandwidth of 570 KHz. The pass band of the UDF module 1922is on the order of 899.915 MHZ to 900.485 MHZ. The Q factor of the UDFmodule 1922 is approximately 1879 (i.e., 900.2 MHZ divided by 570 KHz).

The operation of the UDF module 1922 shall now be described withreference to a Table 1802 (FIG. 18) that indicates example values atnodes in the UDF module 1922 at a number of consecutive time increments.It is assumed in Table 1802 that the UDF module 1922 begins operating attime t−1. As indicated below, the UDF module 1922 reaches steady state afew time units after operation begins. The number of time unitsnecessary for a given UDF module to reach steady state depends on theconfiguration of the UDF module, and will be apparent to persons skilledin the relevant art(s) based on the teachings contained herein.

At the rising edge of φ₁ at time t−1, a switch 1950 in the down-convertand delay module 1924 closes. This allows a capacitor 1952 to charge tothe current value of an

input signal, VI_(t−1), such that node 1902 is at VI_(t−1). This isindicated by cell 1804 in FIG. 18. In effect, the combination of theswitch 1950 and the capacitor 1952 in the down-convert and delay module1924 operates to translate the frequency of the input signal VI to adesired lower frequency, such as IF or baseband. Thus, the value storedin the capacitor 1952 represents an instance of a down-converted imageof the input signal VI.

The manner in which the down-convert and delay module 1924 performsfrequency down-conversion is further described elsewhere in thisapplication, and is additionally described in pending U.S. application“Method and System for Down-Converting Electromagnetic Signals,” Ser.No. 09/176,022, filed Oct. 21, 1998, which is herein incorporated byreference in its entirety.

Also at the rising edge of φ₁ at time t−1, a switch 1958 in the firstdelay module 1928 closes, allowing a capacitor 1960 to charge toVO_(t−1), such that node 1906 is at VO_(t−1). This is indicated by cell1806 in Table 1802. (In practice, VO_(t−1) is undefined at this point.However, for ease of understanding, VO_(t−1) shall continue to be usedfor purposes of explanation.)

Also at the rising edge of φ₁ at time t−1, a switch 1966 in the seconddelay module 1930 closes, allowing a capacitor 1968 to charge to a valuestored in a capacitor 1964. At this time, however, the value incapacitor 1964 is undefined, so the value in capacitor 1968 isundefined. This is indicated by cell 1807 in table 1802.

At the rising edge of φ₂ at time t−1, a switch 1954 in the down-convertand delay module 1924 closes, allowing a capacitor 1956 to charge to thelevel of the capacitor 1952. Accordingly, the capacitor 1956 charges toVI_(t−1) such that node 1904 is at VI_(t−1). This is indicated by cell1810 in Table 1802.

The UDF module 1922 may optionally include a unity gain module 1990Abetween capacitors 1952 and 1956. The unity gain module 1990A operatesas a current source to enable capacitor 1956 to charge without drainingthe charge from capacitor 1952. For a similar reason, the UDF module1922 may include other unity gain modules 1990B-1990G. It should beunderstood that, for many embodiments and applications of the invention,these unity gain modules 1990A-1990G are optional. The structure andoperation of the unity gain modules 1990 will be apparent to personsskilled in the relevant art(s).

Also at the rising edge of φ₂, at time t−1, a switch 1962 in the firstdelay module 1928 closes allowing a capacitor 1964 to charge to thelevel of the capacitor 1900. Accordingly, the capacitor 1964 charges toVO_(t−1) such that node 1908 is at VO_(t−1). This is indicated by cell1814 in Table 1802.

Also at the rising edge of φ₂ at time t−1, a switch 1970 in the seconddelay module 1930 closes, allowing a capacitor 1972 to charge to a valuestored in a capacitor 1968. At this time, however, the value incapacitor 1968 is undefined, so the value in capacitor 1972 isundefined. This is indicated by cell 1815 in table 1802.

At time t, at the rising edge of φ₁, the switch 1950 in the down-convertand delay module 1924 closes. This allows the capacitor 1952 to chargeto VI_(t), such that node 1902 is at VI_(t). This is indicated in cell1816 of Table 1802.

Also at the rising edge of φ1 at time t, the switch 1958 in the firstdelay module 1928 closes, thereby allowing the capacitor 1960 to chargeto VO_(t). Accordingly, node 1906 is at VO_(t). This is indicated incell 1820 in Table 1802.

Further at the rising edge of φ₁ at time t, the switch 1966 in thesecond delay module 1930 closes, allowing a capacitor 1968 to charge tothe level of the capacitor 1964. Therefore, the capacitor 1968 chargesto VO_(t−1), such that node 1910 is at VO_(t−1). This is indicated bycell 1824 in Table 1802.

At the rising edge of φ₂ at time t, the switch 1954 in the down-convertand delay module 1924 closes, allowing the capacitor 1956 to charge tothe level of the capacitor 1952. Accordingly, the capacitor 1956 chargesto VI_(t), such that node 1904 is at VI_(t). This is indicated by cell1828 in Table 1802.

Also at the rising edge of φ₂ at time t, the switch 1962 in the firstdelay module 1928 closes, allowing the capacitor 1964 to charge to thelevel in the capacitor 1960. Therefore, the capacitor 1964 charges toVO_(t), such that node 1908 is at VO_(t). This is indicated by cell 1832in Table 1802.

Further at the rising edge of φ₂ at time t, the switch 1970 in thesecond delay module 1930 closes, allowing the capacitor 1972 in thesecond delay module 1930 to charge to the level of the capacitor 1968 inthe second delay module 1930. Therefore, the capacitor 1972 charges toVO_(t−1), such that node 1912 is at VO_(t−1). This is indicated in cell1836 of FIG. 18.

At time t+1, at the rising edge of φ₁, the switch 1950 in thedown-convert and delay module 1924 closes, allowing the capacitor 1952to charge to VI_(t+1). Therefore, node 1902 is at VI_(t+1), as indicatedby cell 1838 of Table 1802.

Also at the rising edge of φ₁ at time t+1, the switch 1958 in the firstdelay module 1928 closes, allowing the capacitor 1960 to charge toVO_(t+1). Accordingly, node 1906 is at VO_(t+1), as indicated by cell1842 in Table 1802.

Further at the rising edge of φ₁ at time t+1, the switch 1966 in thesecond delay module 1930 closes, allowing the capacitor 1968 to chargeto the level of the capacitor 1964. Accordingly, the capacitor 1968charges to VO_(t), as indicated by cell 1846 of Table 1802.

In the example of FIG. 19, the first scaling module 1932 scales thevalue at node 1908 (i.e., the output of the first delay module 1928) bya scaling factor of −0.1. Accordingly, the value present at node 1914 attime t+1 is −0.1*VO_(t). Similarly, the second scaling module 1934scales the value present at node 1912 (i.e., the output of the secondscaling module 1930) by a scaling factor of −0.8. Accordingly, the valuepresent at node 1916 is −0.8*VO_(t−1) at time t+1.

At time t+1, the values at the inputs of the summer 1926 are: VI_(t) atnode 1904, −0.1*VO_(t) at node 1914, and −0.8*VO_(t−1) at node 1916 (inthe example of FIG. 19, the values at nodes 1914 and 1916 are summed bya second summer 1925, and this sum is presented to the summer 1926).Accordingly, at time t+1, the summer generates a signal equal toVI_(t)−0.1*VO_(t)−0.8*VO_(t−1).

At the rasing edge of φ₁ at time t+1, a switch 1991 in the output sampleand hold module 1936 closes, thereby allowing a capacitor 1992 to chargeto VO_(t+1). Accordingly, the capacitor 1992 charges to VO_(t+1), whichis equal to the sum generated by the adder 1926. As just noted, thisvalue is equal to: VI_(t)−0.1*VO_(t)−0.8*VO_(t−1). This is indicated incell 1850 of Table 1802. This value is presented to the optional outputsmoothing module 1938, which smooths the signal to thereby generate theinstance of the output signal VO_(t+1). It is apparent from inspectionthat this value of VO_(t+1) is consistent with the band pass filtertransfer function of EQ. 1.

Further details of unified down-conversion and filtering as described inthis section are presented in pending U.S. application “IntegratedFrequency Translation And

Selectivity,” Ser. No. 09/175,966, filed Oct. 21, 1998, incorporatedherein by reference in its entirety.

6. Example Application Embodiments of the Invention

As noted above, the UFT module of the present invention is a verypowerful and flexible device. Its flexibility is illustrated, in part,by the wide range of applications in which it can be used. Its power isillustrated, in part, by the usefulness and performance of suchapplications.

Example applications of the UFT module were described above. Inparticular, frequency down-conversion, frequency up-conversion, enhancedsignal reception, and unified down-conversion and filtering applicationsof the UFT module were summarized above, and are further describedbelow. These applications of the UFT module are discussed herein forillustrative purposes. The invention is not limited to these exampleapplications. Additional applications of the UFT module will be apparentto persons skilled in the relevant art(s), based on the teachingscontained herein.

For example, the present invention can be used in applications thatinvolve frequency down-conversion. This is shown in FIG. 1C, forexample, where an example UFT module 115 is used in a down-conversionmodule 114. In this capacity, the UFT module 115 frequency down-convertsan input signal to an output signal. This is also shown in FIG. 7, forexample, where an example UFT module 706 is part of a down-conversionmodule 704, which is part of a receiver 702.

The present invention can be used in applications that involve frequencyup-conversion. This is shown in FIG. 1D, for example, where an exampleUFT module 117 is used in a frequency up-conversion module 116. In thiscapacity, the UFT module 117 frequency up-converts an input signal to anoutput signal. This is also shown in FIG. 8, for example, where anexample UFT module 806 is part of up-conversion module 804, which ispart of a transmitter 802.

The present invention can be used in environments having one or moretransmitters 902 and one or more receivers 906, as illustrated in FIG.9. In such environments, one or more of the transmitters 902 may beimplemented using a UFT module, as shown for example in FIG. 8. Also,one or more of the receivers 906 may be implemented using a UFT module,as shown for example in FIG. 7.

The invention can be used to implement a transceiver. An exampletransceiver 1002 is illustrated in FIG. 10. The transceiver 1002includes a transmitter 1004 and a receiver 1008. Either the transmitter1004 or the receiver 1008 can be implemented using a UFT module.Alternatively, the transmitter 1004 can be implemented using a UFTmodule 1006, and the receiver 1008 can be implemented using a UFT module1010. This embodiment is shown in FIG. 10.

Another transceiver embodiment according to the invention is shown inFIG. 11. In this transceiver 1102, the transmitter 1104 and the receiver1108 are implemented using a single UFT module 1106. In other words, thetransmitter 1104 and the receiver 1108 share a UFT module 1106.

As described elsewhere in this application, the invention is directed tomethods and systems for enhanced signal reception (ESR). Various ESRembodiments include an ESR module (transmit) in a transmitter 1202, andan ESR module (receive) in a receiver 1210. An example ESR embodimentconfigured in this manner is illustrated in FIG. 12.

The ESR module (transmit) 1204 includes a frequency up-conversion module1206. Some embodiments of this frequency up-conversion module 1206 maybe implemented using a UFT module, such as that shown in FIG. 1D.

The ESR module (receive) 1212 includes a frequency down-conversionmodule 1214. Some embodiments of this frequency down-conversion module1214 may be implemented using a UFT module, such as that shown in FIG.1C.

As described elsewhere in this application, the invention is directed tomethods and systems for unified down-conversion and filtering (UDF). Anexample unified down-conversion and filtering module 1302 is illustratedin FIG. 13. The unified down-conversion and filtering module 1302includes a frequency down-conversion module 1304 and a filtering module1306. According to the invention, the frequency down-conversion module1304 and the filtering module 1306 are implemented using a UFT module1308, as indicated in FIG. 13.

Unified down-conversion and filtering according to the invention isuseful in applications involving filtering and/or frequencydown-conversion. This is depicted, for example, in FIGS. 15A-15F. FIGS.15A-15C indicate that unified down-conversion and filtering according tothe invention is useful in applications where filtering precedes,follows, or both precedes and follows frequency down-conversion. FIG.15D indicates

that a unified down-conversion and filtering module 1524 according tothe invention can be utilized as a filter 1522 (i.e., where the extentof frequency down-conversion by the down-converter in the unifieddown-conversion and filtering module 1524 is minimized). FIG. 15Eindicates that a unified down-conversion and filtering module 1528according to the invention can be utilized as a down-converter 1526(i.e., where the filter in the unified down-conversion and filteringmodule 1528 passes substantially all frequencies). FIG. 15F illustratesthat the unified down-conversion and filtering module 1532 can be usedas an amplifier. It is noted that one or more UDF modules can be used inapplications that involve at least one or more of filtering, frequencytranslation, and amplification.

For example, receivers, which typically perform filtering,down-conversion, and filtering operations, can be implemented using oneor more unified down-conversion and filtering modules. This isillustrated, for example, in FIG. 14.

The methods and systems of unified down-conversion and filtering of theinvention have many other applications. For example, as discussedherein, the enhanced signal reception (ESR) module (receive) operates todown-convert a signal containing a plurality of spectrums. The ESRmodule (receive) also operates to isolate the spectrums in thedown-converted signal, where such isolation is implemented via filteringin some embodiments. According to embodiments of the invention, the ESRmodule (receive) is implemented using one or more unifieddown-conversion and filtering (UDF) modules. This is illustrated, forexample, in FIG. 16. In the example of FIG. 16, one or more of the UDFmodules 1610, 1612, 1614 operates to down-convert a received signal. TheUDF modules 1610, 1612, 1614 also operate to filter the down-convertedsignal so as to isolate the spectrum(s) contained therein. As notedabove, the UDF modules 1610, 1612, 1614 are implemented using theuniversal frequency translation (UFT) modules of the invention.

The invention is not limited to the applications of the UFT moduledescribed above. For example, and without limitation, subsets of theapplications (methods and/or structures) described herein (and othersthat would be apparent to persons skilled in the relevant art(s) basedon the herein teachings) can be associated to form useful combinations.

For example, transmitters and receivers are two applications of the UFTmodule. FIG. 10 illustrates a transceiver 1002 that is formed bycombining these two applications of the UFT module, i.e., by combining atransmitter 1004 with a receiver 1008.

Also, ESR (enhanced signal reception) and unified down-conversion andfiltering are two other applications of the UFT module. FIG. 16illustrates an example where ESR and unified down-conversion andfiltering are combined to form a modified enhanced signal receptionsystem.

The invention is not limited to the example applications of the UFTmodule discussed herein. Also, the invention is not limited to theexample combinations of applications of the UFT module discussed herein.These examples were provided for illustrative purposes only, and are notlimiting. Other applications and combinations of such applications willbe apparent to persons skilled in the relevant art(s) based on theteachings contained herein. Such applications and combinations include,for example and without limitation, applications/combinationscomm^(.−)sing and/or involving one or more of: (1) frequencytranslation; (2) frequency down-conversion; (3) frequency up-conversion;(4) receiving; (5) transmitting; (6) filtering; and/or (7) signaltransmission and reception in environments containing potentiallyjamming signals.

Additional example applications are described below.

7. Universal Transmitter

The present invention is directed at a universal transmitter using, inembodiments, two or more UFT modules in a balanced vector modulatorconfiguration. The universal transmitter can be used to create virtuallyevery known and useful waveform used in analog and digitalcommunications applications in wired and wireless markets. Byappropriately selecting the inputs to the universal transmitter, a hostof signals can be synthesized including but not limited to AM, FM, BPSK,QPSK, MSK, QAM, ODFM, multi-tone, and spread-spectrum signals (includingCDMA and frequency hopping). As will be shown, the universal transmittercan up-convert these waveforms using less components than that seen withconventional super-hetrodyne approaches. In other words, the universaltransmitter does not require multiple IF stages (having intermediatefiltering) to up-convert complex waveforms that have demanding spectralgrowth requirements. The elimination of intermediate IF stages reducespart count in the

transmitter and therefore leads to cost savings. As will be shown, thepresent invention achieves these savings without sacrificingperformance.

Furthermore, the use of a balanced configuration means that carrierinsertion can be attenuated or controlled during up-conversion of abaseband signal. Carrier insertion is caused by the variation oftransmitter components (e.g. resistors, capacitors, etc.), whichproduces DC offset voltages throughout the transmitter. Any DC offsetvoltage gets up-converted, along with the baseband signal, and generatesspectral energy (or carrier insertion) at the carrier frequency f_(c).In many transmit applications, it is highly desirable to minimize thecarrier insertion in an up-converted signal because the sideband(s)carry the baseband information and any carrier insertion is wastedenergy that reduces efficiency.

FIGS. 25A-B graphically illustrate carrier insertion in the context ofup-converted signals that carry baseband information in thecorresponding signal sidebands. FIG. 25A depicts an up-converted signal2502 having minimal carrier energy 2504 when compared to sidebands 2506a and 2506 b. In these transmitter applications, the present inventioncan be configured to minimize carrier insertion by limiting the relativeDC offset voltage that is present in the transmitter. Alternatively,some transmit applications require sufficient carrier insertion forcoherent demodulation of the transmitted signal at the receiver. Thisillustrated by FIG. 25B, which shows up-converted signal 2508 havingcarrier energy 2510 that is somewhat larger than sidebands 2512 a and2512 b. In these applications, the present invention can be configuredto introduce a DC offset voltage that generates the desired carrierinsertion.

7.1 Universal Transmitter Having 2 UFT Modules

FIG. 26A illustrates a transmitter 2602 according to embodiments of thepresent invention. Transmitter 2602 includes a balancedmodulator/up-converter 2604, a control signal generator 2642, anoptional filter 2606, and an optional amplifier 2608. Transmitter 2602up-converts a baseband signal 2610 to produce an output signal 2640 thatis conditioned for wireless or wire line transmission. In doing so, thebalanced modulator 2604 receives the baseband signal 2610 and samplesthe baseband signal in a differential and balanced fashion to generate aharmonically rich signal 2638. The harmonically rich signal 2638includes multiple harmonic images, where each image contains thebaseband information in the baseband signal 2610. The optional bandpassfilter 2606 may be

included to select a harmonic of interest (or a subset of harmonics) inthe signal 2558 for transmission. The optional amplifier 2608 may beincluded to amplify the selected harmonic prior to transmission. Theuniversal transmitter is further described at a high level by theflowchart 6200 that is shown in FIG. 62. A more detailed structural andoperational description of the balanced modulator follows thereafter.

Referring to flowchart 6200, in step 6202, the balanced modulator 2604receives the baseband signal 2610.

In step 6204, the balanced modulator 2604 samples the baseband signal ina differential and balanced fashion according to a first and secondcontrol signals that are phase shifted with respect to each other. Theresulting harmonically rich signal 2638 includes multiple harmonicimages that repeat at harmonics of the sampling frequency, where eachimage contains the necessary amplitude and frequency information toreconstruct the baseband signal 2610.

In embodiments of the invention, the control signals include pulseshaving pulse widths (or apertures) that are established to improveenergy transfer to a desired harmonic of the harmonically rich signal.In further embodiments of the invention, DC offset voltages areminimized between sampling modules as indicated in step 6206, therebyminimizing carrier insertion in the harmonic images of the harmonicallyrich signal 2638.

In step 6208, the optional bandpass filter 2606 selects the desiredharmonic of interest (or a subset of harmonics) in from the harmonicallyrich signal 2638 for transmission.

In step 6210, the optional amplifier 2608 amplifies the selectedharmonic(s) prior to transmission.

In step 6212, the selected harmonic(s) is transmitted over acommunications medium.

7.1.1 Balanced Modulator Detailed Description

Referring to the example embodiment shown in FIG. 26A, the balancedmodulator 2604 includes the following components: a buffer/inverter2612; summer amplifiers 2618, 2619; UFT modules 2624 and 2628 havingcontrolled switches 2648 and 2650, respectively; an inductor 2626; ablocking capacitor 2636; and a DC terminal 2611. As stated above, thebalanced modulator 2604 differentially samples the baseband signal 2610to generate a harmonically rich signal 2638. More specifically, the UFTmodules

2624 and 2628 sample the baseband signal in differential fashionaccording to control signals 2623 and 2627, respectively. A DC referencevoltage 2613 is applied to terminal 2611 and is uniformly distributed tothe UFT modules 2624 and 2628. The distributed DC voltage 2613 preventsany DC offset voltages from developing between the UFT modules, whichcan lead to carrier insertion in the harmonically rich signal 2638 asdescribed above. The operation of the balanced modulator 2604 isdiscussed in greater detail with reference to flowchart 6300 (FIG. 63),as follows.

In step 6302, the buffer/inverter 2612 receives the input basebandsignal 2610 and generates input signal 2614 and inverted input signal2616. Input signal 2614 is substantially similar to signal 2610, andinverted signal 2616 is an inverted version of signal 2614. As such, thebuffer/inverter 2612 converts the (single-ended) baseband signal 2610into differential input signals 2614 and 2616 that will be sampled bythe UFT modules. Buffer/inverter 2612 can be implemented using knownoperational amplifier (op amp) circuits, as will be understood by thoseskilled in the arts, although the invention is not limited to thisexample.

In step 6304, the summer amplifier 2618 sums the DC reference voltage2613 applied to terminal 2611 with the input signal 2614, to generate acombined signal 2620. Likewise, the summer amplifier 2619 sums the DCreference voltage 2613 with the inverted input signal 2616 to generate acombined signal 2622. Summer amplifiers 2618 and 2619 can be implementedusing known op amp summer circuits, and can be designed to have aspecified gain or attenuation, including unity gain, although theinvention is not limited to this example. The DC reference voltage 2613is also distributed to the outputs of both UFT modules 2624 and 2628through the inductor 2626 as is shown.

In step 6306, the control signal generator 2642 generates controlsignals 2623 and 2627 that are shown by way of example in FIG. 27B andFIG. 27C, respectively. As illustrated, both control signals 2623 and2627 have the same period T_(S) as a master clock signal 2645 (FIG.27A), but have a pulse width (or aperture) of T_(A). In the example,control signal 2623 triggers on the rising pulse edge of the masterclock signal 2645, and control signal 2627 triggers on the falling pulseedge of the master clock signal 2645. Therefore, control signals 2623and 2627 are shifted in time by 180 degrees relative to each other. Inembodiments of invention, the master clock signal 2645 (and thereforethe control signals

2623 and 2627) have a frequency that is a sub-harmonic of the desiredoutput signal 2640. The invention is not limited to the example of FIGS.27A-27C.

In one embodiment, the control signal generator 2642 includes anoscillator 2646, pulse generators 2644 a and 2644 b, and an inverter2647 as shown. In operation, the oscillator 2646 generates the masterclock signal 2645, which is illustrated in FIG. 27A as a periodic squarewave having pulses with a period of T_(S). Other clock signals could beused including but not limited to sinusoidal waves, as will beunderstood by those skilled in the arts. Pulse generator 2644 a receivesthe master clock signal 2645 and triggers on the rising pulse edge, togenerate the control signal 2623. Inverter 2647 inverts the clock signal2645 to generate an inverted clock signal 2643. The pulse generator 2644b receives the inverted clock signal 2643 and triggers on the risingpulse edge (which is the falling edge of clock signal 2645), to generatethe control signal 2627.

FIG. 74A-E illustrate example embodiments for the pulse generator 2644.FIG. 74A illustrates a pulse generator 7402. The pulse generator 7402generates pulses 7408 having pulse width T_(A) from an input signal7404. Example input signals 7404 and pulses 7408 are depicted in FIGS.74B and 74C, respectively. The input signal 7404 can be any type ofperiodic signal, including, but not limited to, a sinusoid, a squarewave, a saw-tooth wave etc. The pulse width (or aperture) T_(A) of thepulses 7408 is determined by delay 7406 of the pulse generator 7402. Thepulse generator 7402 also includes an optional inverter 7410, which isoptionally added for polarity considerations as understood by thoseskilled in the arts. The example logic and implementation shown for thepulse generator 7402 is provided for illustrative purposes only, and isnot limiting. The actual logic employed can take many forms. Additionalexamples of pulse generation logic are shown in FIGS. 74D and 74E. FIG.74D illustrates a rising edge pulse generator 7412 that triggers on therising edge of input signal 7404. FIG. 74E illustrates a falling edgepulse generator 7416 that triggers on the falling edge of the inputsignal 7404.

In step 6308, the UFT module 2624 samples the combined signal 2620according to the control signal 2623 to generate harmonically richsignal 2630. More specifically, the switch 2648 closes during the pulsewidths T_(A) of the control signal 2623 to sample the combined signal2620 resulting in the harmonically rich signal 2630. FIG. 26Billustrates an exemplary frequency spectrum for the harmonically richsignal 2630 having harmonic

images 2652 a-n. The images 2652 repeat at harmonics of the samplingfrequency 1/T_(s), at infinitum, where each image 2652 contains thenecessary amplitude, frequency, and phase information to reconstruct thebaseband signal 2610. As discussed further below, the relative amplitudeof the frequency images is generally a function of the harmonic numberand the pulse width T_(A). As such, the relative amplitude of aparticular harmonic 2652 can be increased (or decreased) by adjustingthe pulse width T_(A) of the control signal 2623. In general, shorterpulse widths of T_(A) shift more energy into the higher frequencyharmonics, and longer pulse widths of T_(A) shift energy into the lowerfrequency harmonics. The generation of harmonically rich signals bysampling an input signal according to a controlled aperture have beendescribed earlier in this application in the section titled, “FrequencyUp-conversion Using Universal Frequency Translation”, and is illustratedby FIGS. 3-6. A more detailed discussion of frequency up-conversionusing a switch with a controlled sampling aperture is discussed in theco-pending patent application titled, “Method and System for FrequencyUp-Conversion,” Ser. No. 09/176,154, field on Oct. 21, 1998, andincorporated herein by reference.

In step 6310, the UFT module 2628 samples the combined signal 2622according to the control signal 2627 to generate harmonically richsignal 2634. More specifically, the switch 2650 closes during the pulsewidths TA of the control signal 2627 to sample the combined signal 2622resulting in the harmonically rich signal 2634. The harmonically richsignal 2634 includes multiple frequency images of baseband signal 2610that repeat at harmonies of the sampling frequency (1/T_(s)), similar tothat for the harmonically rich signal 2630. However, the images in thesignal 2634 are phase-shifted compared to those in signal 2630 becauseof the inversion of signal 2616 compared to signal 2614, and because ofthe relative phase shift between the control signals 2623 and 2627.

In step 6312, the node 2632 sums the harmonically rich signals 2632 and2634 to generate harmonically rich signal 2633. FIG. 26C illustrates anexemplary frequency spectrum for the harmonically rich signal 2633 thathas multiple images 2654 a-n that repeat at harmonics of the samplingfrequency 1/T_(s). Each image 2654 includes the necessary amplitude,frequency and phase information to reconstruct the baseband signal 2610.The capacitor 2636 operates as a DC blocking capacitor and substantiallypasses the harmonics in the harmonically rich signal 2633 to generateharmonically rich signal 2638 at the output of the modulator 2604.

In step 6208, the optional filter 2606 can be used to select a desiredharmonic image for transmission. This is represented for example by apassband 2656 that selects the harmonic image 2654 c for transmission inFIG. 26C.

An advantage of the modulator 2604 is that it is fully balanced, whichsubstantially minimizes (or eliminates) any DC voltage offset betweenthe two UFT modules 2624 and 2628. DC offset is minimized because thereference voltage 2613 contributes a consistent DC component to theinput signals 2620 and 2622 through the summing amplifiers 2618 and2619, respectively. Furthermore, the reference voltage 2613 is alsodirectly coupled to the outputs of the UFT modules 2624 and 2628 throughthe inductor 2626 and the node 2632. The result of controlling the DCoffset between the UFT modules is that carrier insertion is minimized inthe harmonic images of the harmonically rich signal 2638. As discussedabove, carrier insertion is substantially wasted energy because theinformation for a modulated signal is carried in the sidebands of themodulated signal and not in the carrier. Therefore, it is oftendesirable to minimize the energy at the carrier frequency by controllingthe relative DC offset.

7.1.2 Balanced Modulator Example Signal Diagrams and MathematicalDescription

In order to further describe the invention, FIGS. 27D-27I illustratevarious example signal diagrams (vs. time) that are representative ofthe invention. These signal diagrams are meant for example purposes onlyand are not meant to be limiting. FIG. 27D illustrates a signal 2702that is representative of the input baseband signal 2610 (FIG. 26A).FIG. 27E illustrates a step function 2704 that is an expanded portion ofthe signal 2702 from time to to t1, and represents signal 2614 at theoutput of the buffer/inverter 2612. Similarly, FIG. 27F illustrates asignal 2706 that is an inverted version of the signal 2704, andrepresents the signal 2616 at the inverted output of buffer/inverter2612. For analysis purposes, a step function is a good approximation fora portion of a single bit of data (for the baseband signal 2610) becausethe clock rates of the control signals 2623 and 2627 are significantlyhigher than the data rates of the baseband signal 2610. For example, ifthe data rate is in the KHz frequency range, then the clock rate willpreferably be in MHZ frequency range in order to generate an outputsignal in the Ghz frequency range.

Still referring to FIGS. 27D-I, FIG. 270 illustrates a signal 2708 thatan example of the harmonically rich signal 2630 when the step function2704 is sampled according to the control signal 2623 in FIG. 2711, Thesignal 2708 includes positive pulses 2709 as referenced to the DCvoltage 2613. Likewise, FIG. 27H illustrates a signal 2710 that is anexample of the harmonically rich signal 2634 when the step function 2706is sampled according to the control signal 2627. The signal 2710includes negative pukes 2711 as referenced to the DC voltage 2613, whichare time-shifted relative the positive pulses 2709 in signal 2708.

Still referring to FIGS. 27D-I, the FIG. 271 illustrates a signal 2712that is the combination of signal 2708 (FIG. 27G) and the signal 2710(FIG. 27H), and is an example of the harmonically rich signal 2633 atthe output of the summing node 2632. As illustrated, the signal 2712spends approximately as much time above the DC reference voltage 2613 asbelow the DC reference voltage 2613 over a limited time period. Forexample, over a time period 2714, the energy in the positive pulses 2709a-b is canceled out by the energy in the negative pulses 2711 a-b. Thisis indicative of minimal (or zero) DC offset between the UFT modules2624 and 2628, which results in minimal carrier insertion during thesampling process.

Still referring to FIG. 27I, the time axis of the signal 2712 can bephased in such a manner to represent the waveform as an off function.For such an arrangement, the Fourier series is readily calculated toobtain:

$\begin{matrix}{{I_{c}(t)} = {\sum\limits_{n = 1}^{\infty}{\left( \frac{4\; {{\sin \left( \frac{n\; \pi \; T_{A}}{T_{s}} \right)} \cdot {\sin \left( \frac{n\; \pi}{2} \right)}}}{n\; \pi} \right) \cdot {{\sin\left( \frac{2n\; \pi \; t}{T_{s}} \right)}.}}}} & {{Equation}\mspace{14mu} 1}\end{matrix}$

Where: T_(S)=period of the master clock 2645

-   -   T_(A)=pulse width of the control signals 2623 and 2627    -   N=harmonic number

As shown by Equation 1, the relative amplitude of the frequency imagesis generally a function of the harmonic number n, and the ratio ofT_(A)/T_(S). As indicated, the T_(A)/T_(S) ratio represents the ratio ofthe pulse width of the control signals relative to the period of thesub-harmonic master clock. The T_(A)/T_(S) ratio can be optimized inorder to maximize the amplitude of the frequency image at a givenharmonic. For example, if a

passband waveform is desired to be created at 5× the frequency of thesub-harmonic clock, then a baseline power for that harmonic extractionmay be calculated for the fifth harmonic (n=5) as:

$\begin{matrix}{{I_{c}(t)} = {\left( \frac{4\; {\sin \left( \frac{5\pi \; T_{A}}{T_{s}} \right)}}{5\pi} \right) \cdot {\sin \left( {5\; \omega_{s}\; t} \right)}}} & {{Equation}\mspace{14mu} 2}\end{matrix}$

As shown by Equation 2, lc (t) for the fifth harmonic is a sinusoidalfunction having an amplitude that is proportional to thesin(5πT_(A)/T_(S)). The signal amplitude can be maximized by settingT_(A)= 1/10·T_(S)) so that sin(5πT_(A)/T_(S))=sin(π/2)=1. Doing soresults in the equation:

$\begin{matrix}{\left. {I_{c}(t)} \right|_{n = 5} = {\frac{4}{5\pi}{\left( {\sin \left( {5\omega_{s}t} \right)} \right).}}} & {{Equation}\mspace{14mu} 3}\end{matrix}$

This component is a frequency at 5× of the sampling frequency ofsub-harmonic clock, and can be extracted from the Fourier series via abandpass filter (such as bandpass filter 2606) that is centered around5f_(S). The extracted frequency component can then be optionallyamplified by the amplifier 2608 prior to transmission on a wireless orwire-line communications channel or channels.

Equation 3 can be extended to reflect the inclusion of a message signalas illustrated by equation 4 below:

$\begin{matrix}{{{{m(t)} \cdot {I_{c}(t)}}|_{\theta = {\theta {(t)}}}^{n = 5}} = {\frac{4 \cdot {m(t)}}{5\pi}{\left( {\sin \left( {{5\omega_{s}t} + {5\; {\theta (t)}}} \right)} \right).}}} & {{Equation}\mspace{14mu} 4}\end{matrix}$

Equation 4 illustrates that a message signal can be carried inharmonically rich signals 2633 such that both amplitude and phase can bemodulated. In other words, m(t) is modulated for amplitude and θ(t) ismodulated for phase. In such cases, it should be noted that θ(t) isaugmented modulo n while the amplitude modulation m(t) is simply scaled.Therefore, complex waveforms may be reconstructed from their Fourierseries with multiple aperture UFT combinations.

As discussed above, the signal amplitude for the 5th harmonic wasmaximized by setting the sampling aperture width T_(A)= 1/10 T_(S) whereT_(S) is the period of the master clock signal. This can be restated andgeneralized as setting T_(A)=½ the period (or π

radians) at the harmonic of interest. In other words, the signalamplitude of any harmonic n can be maximized by sampling the inputwaveform with a sampling aperture of TA=V2 the period of the harmonic ofinterest (n). Based on this discussion, it is apparent that varying theaperture changes the harmonic and amplitude content of the outputwaveform, For example, if the sub-harmonic clock has a frequency of 200MHZ, then the fifth harmonic is at 1 Ghz. The amplitude of the fifthharmonic is maximized by setting the aperture width T_(A)=500picoseconds, which equates to ½ the period (or π radians) at 1 Ghz.

FIG. 27J depicts a frequency plot 2716 that graphically illustrates theeffect of varying the sampling aperture of the control signals on theharmonically rich signal 2633 given a 200 MHZ harmonic clock. Thefrequency plot 2716 compares two frequency spectrums 2718 and 2720 fordifferent control signal apertures given a 200 MHZ clock. Morespecifically, the frequency spectrum 2718 is an example spectrum forsignal 2633 given the 200 MHZ clock with the aperture T_(A)=500 psec(where 500 psec is it radians at the 5th harmonic of 1 GHz). Similarly,the frequency spectrum 2720 is an example spectrum for signal 2633 givena 200 MHZ clock that is a square wave (so T_(A)=5000 psec). The spectrum2718 includes multiple harmonics 2718 a-i, and the frequency spectrum2720 includes multiple harmonics 2720 a-e. [It is noted that spectrum2720 includes only the odd harmonics as predicted by Fourier analysisfor a square wave.] At 1 Ghz (which is the 5th harmonic), the signalamplitude of the two frequency spectrums 2718 e and 2720 c areapproximately equal. However, at 200 MHZ, the frequency spectrum 2718 ahas a much lower amplitude than the frequency spectrum 2720 a, andtherefore the frequency spectrum 2718 is more efficient than thefrequency spectrum 2720, assuming the desired harmonic is the 5thharmonic. In other words, assuming 1 Ghz is the desired harmonic, thefrequency spectrum 2718 wastes less energy at the 200 MHZ fundamentalthan does the frequency spectrum 2718.

7.1.3 Balanced Modulator Having a Shunt Configuration

FIG. 56A illustrates a universal transmitter 5600 that is a secondembodiment of a universal transmitter having two balanced UFT modules ina shunt configuration. (In contrast, the balanced modulator 2604 can bedescribed as having a series configuration based on the orientation ofthe UFT modules.) Transmitter 5600 includes a balanced modulator 5601,the control signal generator 2642, the optional bandpass filter 2606,and

the optional amplifier 2608. The transmitter 5600 up-converts a basebandsignal 5602 to produce an output signal 5636 that is conditioned forwireless or wire line transmission. In doing so, the balanced modulator5601 receives the baseband signal 5602 and shunts the baseband signal toground in a differential and balanced fashion to generate a harmonicallyrich signal 5634. The harmonically rich signal 5634 includes multipleharmonic images, where each image contains the baseband information inthe baseband signal 5602. In other words, each harmonic image includesthe necessary amplitude, frequency, and phase information to reconstructthe baseband signal 5602. The optional bandpass filter 2606 may beincluded to select a harmonic of interest (or a subset of harmonics) inthe signal 5634 for transmission. The optional amplifier 2608 may beincluded to amplify the selected harmonic prior to transmission,resulting in the output signal 5636.

The balanced modulator 5601 includes the following components: abuffer/inverter 5604; optional impedances 5610, 5612; UFT modules 5616and 5622 having controlled switches 5618 and 5624, respectively;blocking capacitors 5628 and 5630; and a terminal 5620 that is tied toground. As stated above, the balanced modulator 5601 differentiallyshunts the baseband signal 5602 to ground, resulting in a harmonicallyrich signal 5634. More specifically, the UFT modules 5616 and 5622alternately shunts the baseband signal to terminal 5620 according tocontrol signals 2623 and 2627, respectively. Terminal 5620 is tied toground and prevents any DC offset voltages from developing between theUFT modules 5616 and 5622. As described above, a DC offset voltage canlead to undesired carrier insertion. The operation of the balancedmodulator 5601 is described in greater detail according to the flowchart6400 (FIG. 64) as follows.

In step 6402, the buffer/inverter 5604 receives the input basebandsignal 5602 and generates I signal 5606 and inverted I signal 5608. Isignal 5606 is substantially similar to the baseband signal 5602, andthe inverted I signal 5608 is an inverted version of signal 5602. Assuch, the buffer/inverter 5604 converts the (single-ended) basebandsignal 5602 into differential signals 5606 and 5608 that are sampled bythe UFT modules. Buffer/inverter 5604 can be implemented using knownoperational amplifier (op amp) circuits, as will be understood by thoseskilled in the arts, although the invention is not limited to thisexample.

In step 6404, the control signal generator 2642 generates controlsignals 2623 and 2627 from the master clock signal 2645. Examples of themaster clock signal 2645, control signal 2623, and control signal 2627are shown in FIGS. 27A-C, respectively. As illustrated, both controlsignals 2623 and 2627 have the same period T_(S) as a master clocksignal 2645, but have a pulse width (or aperture) of TA. Control signal2623 triggers on the rising pulse edge of the master clock signal 2645,and control signal 2627 triggers on the falling pulse edge of the masterclock signal 2645. Therefore, control signals 2623 and 2627 are shiftedin time by 180 degrees relative to each other. A specific embodiment ofthe control signal generator 2642 is illustrated in FIG. 26A, and wasdiscussed in detail above.

In step 6406, the UFT module 5616 shunts the signal 5606 to groundaccording to the control signal 2623, to generate a harmonically richsignal 5614. More specifically, the switch 5618 closes and shorts thesignal 5606 to ground (at terminal 5620) during the aperture width TA ofthe control signal 2623, to generate the harmonically rich signal 5614.FIG. 56B illustrates an exemplary frequency spectrum for theharmonically rich signal 5618 having harmonic images 5650 a-n. Theimages 5650 repeat at harmonics of the sampling frequency 1/T_(S), atinfinitum, where each image 5650 contains the necessary amplitude,frequency, and phase information to reconstruct the baseband signal5602. The generation of harmonically rich signals by sampling an inputsignal according to a controlled aperture have been described earlier inthis application in the section titled, “Frequency Up-conversion UsingUniversal Frequency Translation”, and is illustrated by FIGS. 3-6. Amore detailed discussion of frequency up-conversion using a switch witha controlled sampling aperture is discussed in the co-pending patentapplication titled, “Method and System for Frequency Up-Conversion,”Ser. No. 09/176,154, field on Oct. 21, 1998, and incorporated herein byreference.

The relative amplitude of the frequency images 5650 is generally afunction of the harmonic number and the pulse width T_(A). As such, therelative amplitude of a particular harmonic 5650 can be increased (ordecreased) by adjusting the pulse width TA of the control signal 2623.In general, shorter pulse widths of T_(A) shift more energy into thehigher frequency harmonics, and longer pulse widths of T_(A) shiftenergy into the lower frequency harmonics. Additionally, the relativeamplitude of a particular harmonic 5650 can also be adjusted byadding/tuning an optional impedance 5610. Impedance 5610

operates as a filter that emphasizes a particular harmonic in theharmonically rich signal 5614.

In step 6408, the UFT module 5622 shunts the inverted signal 5608 toground according to the control signal 2627, to generate a harmonicallyrich signal 5626. More specifically, the switch 5624 closes during thepulse widths T_(A) and shorts the inverted I signal 5608 to ground (atterminal 5620), to generate the harmonically rich signal 5626. At anygiven time, only one of input signals 5606 or 5608 is shorted to groundbecause the pulses in the control signals 2623 and 2627 are phaseshifted with respect to each other, as shown in FIGS. 27B and 27C.

The harmonically rich signal 5626 includes multiple frequency images ofbaseband signal 5602 that repeat at harmonics of the sampling frequency(1/T_(S)), similar to that for the harmonically rich signal 5614.However, the images in the signal 5626 are phase-shifted compared tothose in signal 5614 because of the inversion of the signal 5608compared to the signal 5606, and because of the relative phase shiftbetween the control signals 2623 and 2627. The optional impedance 5612can be included to emphasis a particular harmonic of interest, and issimilar to the impedance 5610 above.

In step 6410, the node 5632 sums the harmonically rich signals 5614 and5626 to generate the harmonically rich signal 5634. The capacitors 5628and 5630 operate as blocking capacitors that substantially pass therespective harmonically rich signals 5614 and 5626 to the node 5632.(The capacitor values may be chosen to substantially block basebandfrequency components as well.) FIG. 56C illustrates an exemplaryfrequency spectrum for the harmonically rich signal 5634 that hasmultiple images 5652 a-n that repeat at harmonics of the samplingfrequency 1/T_(S). Each image 5652 includes the necessary amplitude,frequency, and phase information to reconstruct the baseband signal5602. The optional filter 2606 can be used to select the harmonic imageof interest for transmission. This is represented by a passband 5656that selects the harmonic image 5632 c for transmission.

An advantage of the modulator 5601 is that it is fully balanced, whichsubstantially minimizes (or eliminates) any DC voltage offset betweenthe two UFT modules 5612 and 5614. DC offset is minimized because theUFT modules 5616 and 5622 are both connected to ground at terminal 5620.The result of controlling the DC offset between the UFT modules is thatcarrier insertion is minimized in the harmonic

images of the harmonically rich signal 5634. As discussed above, carrierinsertion is substantially wasted energy because the information for amodulated signal is carried in the sidebands of the modulated signal andnot in the carrier. Therefore, it is often desirable to minimize theenergy at the earlier frequency by controlling the relative DC offset.

7.1.4 Balanced Modulator FET Configuration

As described above, the balanced modulators 2604 and 5601 utilize twobalanced UFT modules to sample the input baseband signals to generateharmonically rich signals that contain the up-converted basebandinformation. More specifically, the UFT modules include controlledswitches that sample the baseband signal in a balanced and differentialfashion. FIGS. 26D and 56D illustrate embodiments of the controlledswitch in the UFT module.

FIG. 26D illustrates an example embodiment of the modulator 2604 (FIG.26B) where the controlled switches in the UFT modules are field effecttransistors (FET). More specifically, the controlled switches 2648 and2628 are embodied as FET 2658 and FET 2660, respectively. The FET 2658and 2660 are oriented so that their gates are controlled by the controlsignals 2623 and 2627, so that the control signals control the FETconductance. For the FET 2658, the combined baseband signal 2620 isreceived at the source of the FET 2658 and is sampled according to thecontrol signal 2623 to produce the harmonically rich signal 2630 at thedrain of the FET 2658. Likewise, the combined baseband signal 2622 isreceived at the source of the FET 2660 and is sampled according to thecontrol signal 2627 to produce the harmonically rich signal 2634 at thedrain of FET 2660. The source and drain orientation that is illustratedis not limiting, as the source and drains can be switched for most FETs.In other words, the combined baseband signal can be received at thedrain of the FETs, and the harmonically rich signals can be taken fromthe source of the FETs, as will be understood by those skilled in therelevant arts.

FIG. 56D illustrates an embodiment of the modulator 5600 (FIG. 56) wherethe controlled switches in the UFT modules are field effect transistors(FET). More specifically, the controlled switches 5618 and 5624 areembodied as FET 5636 and FET 5638, respectively. The FETs 5636 and 5638are oriented so that their gates are controlled by the control signals2623 and 2627, respectively, so that the control signals determine FETconductance. For the FET 5636, the baseband signal 5606 is received atthe source

of the FET 5636 and shunted to ground according to the control signal2623, to produce the harmonically rich signal 5614. Likewise, thebaseband signal 5608 is received at the source of the FET 5638 and isshunted to grounding according to the control signal 2627, to producethe harmonically rich signal 5626. The source and drain orientation thatis illustrated is not limiting, as the source and drains can be switchedfor most FETs, as will be understood by those skilled in the relevantarts.

7.1.5 Universal Transmitter Configured for Carrier Insertion

As discussed above, the transmitters 2602 and 5600 have a balancedconfiguration that substantially eliminates any DC offset and results inminimal carrier insertion in the output signal 2640. Minimal carrierinsertion is generally desired for most applications because the carriersignal carries no information and reduces the overall transmitterefficiency. However, some applications require the received signal tohave sufficient carrier energy for the receiver to extract the carrierfor coherent demodulation. In support thereof, the present invention canbe configured to provide the necessary carrier insertion by implementinga DC offset between the two sampling UFT modules.

FIG. 28A illustrates a transmitter 2802 that up-converts a basebandsignal 2806 to an output signal 2822 having carrier insertion. As isshown, the transmitter 2802 is similar to the transmitter 2602 (FIG.26A) with the exception that the up-converter/modulator 2804 isconfigured to accept two DC references voltages. In contrast, modulator2604 was configured to accept only one DC reference voltage. Morespecifically, the modulator 2804 includes a terminal 2809 to accept a DCreference voltage 2808, and a terminal 2813 to accept a DC referencevoltage 2814. Vr 2808 appears at the UFT module 2624 though summeramplifier 2618 and the inductor 2810. Vr 2814 appears at UFT module 2628through the summer amplifier 2619 and the inductor 2816. Capacitors 2812and 2818 operate as blocking capacitors. If Vr 2808 is different from Vr2814 then a DC offset voltage will be exist between UFT module 2624 andUFT module 2628, which will be up-converted at the carrier frequency inthe harmonically rich signal 2820. More specifically, each harmonicimage in the harmonically rich signal 2820 will include a carrier signalas depicted in FIG. 28B.

FIG. 28B illustrates an exemplary frequency spectrum for theharmonically rich signal 2820 that has multiple harmonic images 2824a-n. In addition to carrying the baseband information in the sidebands,each harmonic image 2824 also includes a carrier

signal 2826 that exists at respective harmonic of the sampling frequency1/T_(S). The amplitude of the carrier signal increases with increasingDC offset voltage. Therefore, as the difference between Vr 2808 and Vr2814 widens, the amplitude of each carrier signal 2826 increases.Likewise, as the difference between Vr 2808 and Vr 2814 shrinks, theamplitude of each carrier signal 2826 shrinks. As with transmitter 2802,the optional bandpass filter 2606 can be included to select a desiredharmonic image for transmission. This is represented by passband 2828 inFIG. 28B.

7.2 Universal Transmitter in I Q Configuration:

As described above, the balanced modulators 2604 and 5601 up-convert abaseband signal to a harmonically rich signal having multiple harmonicimages of the baseband information. By combining two balancedmodulators, IQ configurations can be formed for up-converting I and Qbaseband signals. In doing so, either the (series type) balancedmodulator 2604 or the (shunt type) balanced modulator can be utilized.IQ modulators having both series and shunt configurations are describedbelow.

7.2.1 IQ Transmitter Using Series-Type Balanced Modulator

FIG. 29 illustrates an IQ transmitter 2920 with an in-phase (I) andquadrature (Q) configuration according to embodiments of the invention.The transmitter 2920 includes an IQ balanced modulator 2910, an optionalfilter 2914, and an optional amplifier 2916. The transmitter 2920 isuseful for transmitting complex I Q waveforms and does so in a balancedmanner to control DC offset and carrier insertion. In doing so, themodulator 2910 receives an I baseband signal 2902 and a Q basebandsignal 2904 and up-converts these signals to generate a combinedharmonically rich signal 2912. The harmonically rich signal 2912includes multiple harmonics images, where each image contains thebaseband information in the I signal 2902 and the Q signal 2904. Theoptional bandpass filter 2914 may be included to select a harmonic ofinterest (or subset of harmonics) from the signal 2912 for transmission.The optional amplifier 2916 may be included to amplify the selectedharmonic prior to transmission, to generate the Q output signal 2918.

As stated above, the balanced IQ modulator 2910 up-converts the Ibaseband signal 2902 and the Q baseband signal 2904 in a balanced mannerto generate the combined harmonically rich signal 2912 that carriers theI and Q baseband information. To do so, the modulator 2910 utilizes twobalanced modulators 2604 from FIG. 26A, a

signal combiner 2908, and a DC terminal 2907. The operation of thebalanced modulator 2910 and other circuits in the transmitter isdescribed according to the flowchart 6500 in FIG. 65, as follows.

In step 6502, the IQ modulator 2910 receives the I baseband signal 2902and the Q baseband signal 2904.

In step 6504, the I balanced modulator 2604 a samples the I basebandsignal 2902 in a differential fashion using the control signals 2623 and2627 to generate a harmonically rich signal 2911 a. The harmonicallyrich signal 2911 a contains multiple harmonic images of the I basebandinformation, similar to the harmonically rich signal 2630 in FIG. 26B.

In step 6506, the balanced modulator 2604 b samples the Q basebandsignal 2904 in a differential fashion using control signals 2623 and2627 to generate harmonically rich signal 2911 b, where the harmonicallyrich signal 2911 b contains multiple harmonic images of the Q basebandsignal 2904. The operation of the balanced modulator 2604 and thegeneration of harmonically rich signals was fully described above andillustrated in FIGS. 26A-C, to which the reader is referred for furtherdetails.

In step 6508, the DC terminal 2907 receives a DC voltage 2906 that isdistributed to both modulators 2604 a and 2604 b. The DC voltage 2906 isdistributed to both the input and output of both UFT modules 2624 and2628 in each modulator 2604. This minimizes (or prevents) DC offsetvoltages from developing between the four UFT modules, and therebyminimizes or prevents any carrier insertion during the sampling steps6504 and 6506.

In step 6510, the 90 degree signal combiner 2908 combines theharmonically rich signals 2911 a and 2911 b to generate IQ harmonicallyrich signal 2912. This is further illustrated in FIGS. 30A-C. FIG. 30Adepicts an exemplary frequency spectrum for the harmonically rich signal2911 a having harmonic images 3002 a-n. The images 3002 repeat atharmonics of the sampling frequency 1/T_(S), where each image 3002contains the necessary amplitude and frequency information toreconstruct the 1 baseband signal 2902. Likewise, FIG. 30B depicts anexemplary frequency spectrum for the harmonically rich signal 2911 bhaving harmonic images 3004 a-n. The harmonic images 3004 a-n alsorepeat at harmonics of the sampling frequency 1/T_(S), where each image3004 contains the necessary amplitude, frequency, and phase informationto reconstruct the Q baseband

signal 2904. FIG. 30C illustrates an exemplary frequency spectrum forthe combined harmonically rich signal 2912 having images 3006. Eachimage 3006 carries the I baseband information and the Q basebandinformation from the corresponding images 3002 and 3004, respectively,without substantially increasing the frequency bandwidth occupied byeach harmonic 3006. This can occur because the signal combiner 2908phase shifts the Q signal 2911 b by 90 degrees relative to the I signal2911 a. The result is that the images 3002 a-n and 3004 a-n effectivelyshare the signal bandwidth do to their orthogonal relationship. Forexample, the images 3002 a and 3004 a effectively share the frequencyspectrum that is represented by the image 3006 a.

In step 6512, the optional filter 2914 can be included to select aharmonic of interest, as represented by the passband 3008 selecting theimage 3006 c in FIG. 30 c.

In step 6514, the optional amplifier 2916 can be included to amplify theharmonic (or harmonics) of interest prior to transmission.

In step 6516, the selected harmonic (or harmonics) is transmitted over acommunications medium.

FIG. 31A illustrates a transmitter 3108 that is a second embodiment foran I Q transmitter having a balanced configuration. Transmitter 3108 issimilar to the transmitter 2920 except that the 90 degree phase shiftbetween the I and Q channels is achieved by phase shifting the controlsignals instead of using a 90 degree signal combiner to combine theharmonically rich signals. More specifically, delays 3104 a and 3104 bdelay the control signals 2623 and 2627 for the Q channel modulator 2604b by 90 degrees relative the control signals for the I channel modulator2604 a. As a result, the Q modulator 2604 b samples the Q basebandsignal 2904 with 90 degree delay relative to the sampling of the Ibaseband signal 2902 by the I channel modulator 2604 a. Therefore, the Qharmonically rich signal 2911 b is phase shifted by 90 degrees relativeto the I harmonically rich signal. Since the phase shift is achievedusing the control signals, an in-phase signal combiner 3106 combines theharmonically rich signals 2911 a and 2911 b, to generate theharmonically rich signal 2912.

FIG. 31B illustrates a transmitter 3118 that is similar to transmitter3108 in FIG. 31A. The difference being that the transmitter 3118 has amodulator 3120 that utilizes a summing node 3122 to sum the signals 2911a and 2911 b instead of the in-phase signal combiner 3106 that is usedin modulator 3102 of transmitter 3108.

FIG. 55A-55D illustrate various detailed circuit implementations of thetransmitter 2920 in FIG. 29. These circuit implementations are meant forexample purposes only, and are not meant to be limiting.

FIG. 55A illustrates I input circuitry 5502 a and Q input circuitry 5502b that receive the I and Q input signals 2902 and 2904, respectively.

FIG. 55B illustrates the I channel circuitry 5506 that processes an Idata 5504 a from the I input circuit 5502 a.

FIG. 55C illustrates the Q channel circuitry 5508 that processes the Qdata 5504 b from the Q input circuit 5502 b.

FIG. 55D illustrates the output combiner circuit 5512 that combines theI channel data 5507 and the Q channel data 5510 to generate the outputsignal 2918.

7.2.2. IQ Transmitter Using Shunt-Type Balanced Modulator

FIG. 57 illustrates an IQ transmitter 5700 that is another IQtransmitter embodiment according to the present invention. Thetransmitter 5700 includes an IQ balanced modulator 5701, an optionalfilter 5712, and an optional amplifier 5714. During operation, themodulator 5701 up-converts an I baseband signal 5702 and a Q basebandsignal 5704 to generate a combined harmonically rich signal 5711. Theharmonically rich signal 5711 includes multiple harmonics images, whereeach image contains the baseband information in the I signal 5702 andthe Q signal 5704. The optional bandpass filter 5712 may be included toselect a harmonic of interest (or subset of harmonics) from theharmonically rich signal 5711 for transmission. The optional amplifier5714 may be included to amplify the selected harmonic prior totransmission, to generate the IQ output signal 5716.

The IQ modulator 5701 includes two balanced modulators 5601 from FIG.56, and a 90 degree signal combiner 5710 as shown. The operation of theIQ modulator 5701 is described in reference to the flowchart 6600 (FIG.66), as follows. The order of the steps in flowchart 6600 is notlimiting.

In step 6602, the balanced modulator 5701 receives the I baseband signal5702 and the Q baseband signal 5704.

In step 6604, the balanced modulator 5601 a differentially shunts the Ibaseband signal 5702 to ground according the control signals 2623 and2627, to generate a harmonically rich signal 5706. More specifically,the UFT modules 5616 a and 5622 a alternately shunt the I basebandsignal and an inverted version of the I baseband signal to groundaccording to the control signals 2623 and 2627, respectively. Theoperation of the balanced modulator 5601 and the generation ofharmonically rich signals was fully described above and is illustratedin FIGS. 56A-C, to which the reader is referred for further details. Assuch, the harmonically rich signal 5706 contains multiple harmonicimages of the I baseband information as described above.

In step 6606, the balanced modulator 5601 b differentially shunts the Qbaseband signal 5704 to ground according to control signals 2623 and2627, to generate harmonically rich signal 5708. More specifically, theUFT modules 5616 b and 5622 b alternately shunt the Q baseband signaland an inverted version of the Q baseband signal to ground, according tothe control signals 2623 and 2627, respectively. As such, theharmonically rich signal 5708 contains multiple harmonic images thatcontain the Q baseband information.

In step 6608, the 90 degree signal combiner 5710 combines theharmonically rich signals 5706 and 5708 to generate IQ harmonically richsignal 5711. This is further illustrated in FIGS. 58A-C. FIG. 58Adepicts an exemplary frequency spectrum for the harmonically rich signal5706 having harmonic images 5802 a-n. The harmonic images 5802 repeat atharmonics of the sampling frequency 1/T_(S), where each image 5802contains the necessary amplitude, frequency, and phase information toreconstruct the I baseband signal 5702. Likewise, FIG. 58B depicts anexemplary frequency spectrum for the harmonically rich signal 5708having harmonic images 5804 a-n. The harmonic images 5804 a-n alsorepeat at harmonics of the sampling frequency 1/T_(S), where each image5804 contains the necessary amplitude, frequency, and phase informationto reconstruct the Q baseband signal 5704. FIG. 58C illustrates anexemplary frequency spectrum for the IQ harmonically rich signal 5711having images 5806 a-n. Each image 5806 carries the I basebandinformation and the Q baseband information from the corresponding images5802 and 5804, respectively, without substantially increasing thefrequency bandwidth occupied by each image 5806. This can occur becausethe signal combiner 5710 phase shifts the Q signal 5708 by 90 degreesrelative to the I signal 5706.

Inn step 6610, the optional filter 5712 may be included to select aharmonic of interest, as represented by the passband 5808 selecting theimage 5806 c in FIG. 58C.

In step 6612, the optional amplifier 5714 can be included to amplify theselected harmonic image 5806 prior to transmission.

In step 6614, the selected harmonic (or harmonics) is transmitted over acommunications medium.

FIG. 59 illustrates a transmitter 5900 that is another embodiment for anI Q transmitter having a balanced configuration. Transmitter 5900 issimilar to the transmitter 5700 except that the 90 degree phase shiftbetween the I and Q channels is achieved by phase shifting the controlsignals instead of using a 90 degree signal combiner to combine theharmonically rich signals. More specifically, delays 5904 a and 5904 bdelay the control signals 2623 and 2627 for the Q channel modulator 5601b by 90 degrees relative the control signals for the I channel modulator5601 a. As a result, the Q modulator 5601 b samples the Q basebandsignal 5704 with a 90 degree delay relative to the sampling of the Ibaseband signal 5702 by the I channel modulator 5601 a. Therefore, the Qharmonically rich signal 5708 is phase shifted by 90 degrees relative tothe I harmonically rich signal 5706. Since the phase shift is achievedusing the control signals, an in-phase signal combiner 5906 combines theharmonically rich signals 5706 and 5708, to generate the harmonicallyrich signal 5711.

FIG. 60 illustrates a transmitter 6000 that is similar to transmitter5900 in FIG. 59. The difference being that the transmitter 6000 has abalanced modulator 6002 that utilizes a summing node 6004 to sum the Iharmonically rich signal 5706 and the Q harmonically rich signal 5708instead of the in-phase signal combiner 5906 that is used in themodulator 5902 of transmitter 5900. The 90 degree phase shift betweenthe I and Q channels is implemented by delaying the Q clock signalsusing 90 degree delays 5904, as shown.

7.2.3 IQ Transmitters Configured for Carrier Insertion

The transmitters 2920 (FIG. 29) and 3108 (FIG. 31A) have a balancedconfiguration that substantially eliminates any DC offset and results inminimal carrier insertion in the IQ output signal 2918. Minimal carrierinsertion is generally desired for most applications because the carriersignal carries no information and reduces the overall transmitterefficiency. However, some applications require the received signal tohave sufficient carrier energy for the receiver to extract the carrierfor coherent demodulation. In support thereof, FIG. 32 illustrates atransmitter 3202 to provide any necessary carrier insertion byimplementing a DC offset between the two sets of sampling UFT modules.

Transmitter 3202 is similar to the transmitter 2920 with the exceptionthat a modulator 3204 in transmitter 3202 is configured to accept two DCreference voltages so that the I channel modulator 2604 a can be biasedseparately from the Q channel modulator 2604 b. More specifically,modulator 3204 includes a terminal 3206 to accept a DC voltage reference3207, and a terminal 3208 to accept a DC voltage reference 3209. Voltage3207 biases the UFT modules 2624 a and 2628 a in the I channel modulator2604 a. Likewise, voltage 3209 biases the UFT modules 2624 b and 2628 bin the Q channel modulator 2604 b. When voltage 3207 is different fromvoltage 3209, then a DC offset will appear between the I channelmodulator 2604 a and the Q channel modulator 2604 b, which results incarrier insertion in the IQ harmonically rich signal 2912. The relativeamplitude of the carrier frequency energy increases in proportion to theamount of DC offset.

FIG. 33 illustrates a transmitter 3302 that is a second embodiment of anIQ transmitter having two DC terminals to cause DC offset, and thereforecarrier insertion. Transmitter 3302 is similar to transmitter 3202except that the 90 degree phase shift between the I and Q channels isachieved by phase shifting the control signals, similar to that done intransmitter 3108. More specifically, delays 3304 a and 3304 b phaseshift the control signals 2623 and 2627 for the Q channel modulator 2604b relative to those of the I channel modulator 2604 a. As a result, theQ modulator 2604 b samples the Q baseband signal 2904 with 90 degreedelay relative to the sampling of the I baseband signal 2902 by the Ichannel modulator 2604 a. Therefore, the Q harmonically rich signal 2911b is phase shifted by 90 degrees relative to the I harmonically richsignal, which is then combined by the in-phase combiner 3306.

7.2.4. Balanced IQ Differential Modulator

FIG. 75 illustrates a balanced IQ Differential Modulator (ortransmitter) 7500 according to embodiments of the present invention. Themodulator 7500 receives a differential in-phase signal 7502 anddifferential quadrature signal 7504, and up-converts

the differential in-phase and quadrature signals 7502 and 7504 togenerate an IQ output signal 7514 that is applied across the load 7512.The IQ output signal 7514 includes a plurality of harmonic images, whereeach harmonic image contains the baseband information in the I basebandsignal 7502 and the Q baseband signal 7504. In other words, eachharmonic image in the IQ output signal 7514 contains the necessaryamplitude, frequency, and phase information to reconstruct the Ibaseband signal 7502 and the Q baseband signal 7504. The invention isnot limited to using a resistor for the load 7512. Other types of loadscould be used, including reactive loads, and resistive reactivenetworks, as will be understood by those skilled in the arts.

The IQ Differential Modulator 7500 includes a differential I channel7516 a and a differential Q channel 7516 b, the outputs of which arecombined at summing nodes 7518 a and 7518 b so as to form the outputsignal 7514. The differential I channel 7516 a includes impedances 7508a and 7508 b, a FET device 7510 a, and a control signal generator 7506a. The FET device 7510 a is configured so that its source and drain areconnected across the outputs of the impedances 7508 a and 7508 b. Thegate of the FET device 7510 a is driven by a control signal 7507 a fromthe control signal generator 7506 a. Likewise, the differential Qchannel 7516 b includes impedances 7508 c and 7508 d, a FET device 7510b, and a control signal generator 7506 b. The FET device 7510 b isconfigured so that its source and drain are connected across respectiveoutputs of the impedances 7508 c and 7508 d. The gate of the FET device7510 b is driven by a control signal 7507 b from the control signalgenerator 7506 b. In embodiments, the impedances 7508 are designed to below impedance at DC, but high impedance at the output frequency ofinterest. For example, the impedances can be inductors that provide alow impedance DC path, but are high impedance at frequencies other thanDC.

The control signal generators 7506 a and 7506 b generate respectivecontrol signals 7507 a and 7507 b having a plurality of pulses. FIG. 76Afurther illustrates control signals 7507 a and 7507 b having a pluralityof pulses that are approximately 270 degrees out of phase with respectto each other. In other embodiments, the pulses are out of phase witheach other by other amounts, such as but not limited to 180 degrees. Inembodiments of the invention, the control signals 7507 a and 7507 binclude pulses having pulse widths (or apertures) that are establishedto improve energy transfer to a desired harmonic of the plurality ofharmonics in the IQ output signal 7514.

Still referring to FIG. 76A, the control signals 7507 a and 7507 b areillustrated to have a sampling period of T_(S), and a pulse width ofT_(A). As will be discussed below, the sampling period T_(S) determinesthe harmonic frequency spacing between harmonics of the IQ output signal7514. Whereas, the pulse width T_(A) determines the relative energycontent that is up-converted into the harmonics of the IQ output signal7514. In embodiments, the sampling period T_(S) is determined so thatthe sampling is performed at a sub-harmonic of the RF input signal. Inembodiments, the pulse width T_(A) is determined to be a ½ sine wavewavelength (or ½λ) of the desired output frequency.

IQ Differential Modulator 7500 operates in a balanced fashion, and theoperation of the IQ differential modulator 7500 is described as follows.

In the I channel 7516 a, the impedances 7508 a and 7508 b differentiallyreceive the differential I signal 7502. The FET device 7510 a shorts (orsamples) the: outputs of the impedances 7508 a and 7508 b according tothe pulses of the control signal 7507 a to produce an I output signal7511. The I output signal 7511 includes a plurality of up-convertedharmonic images, where each harmonic image includes the basebandinformation in the baseband I signal 7502. Likewise, the FET device 7510b shorts (or samples) the output of the impedances 7508 c and 7508 daccording to the pulses of the control signal 7507 b to produce the Qoutput signal 7513. The Q output signal 7513 includes a plurality ofup-converted harmonic images, where each harmonic image includes thebaseband information in the baseband Q signal 7504.

The I output signal 7511 and the Q output signal 7513 are combined atthe summing nodes 7518 a and 7518 b, to produce the IQ output signal7514. More particularly, the I output signal 7511 and the Q outputsignal 7513 are directly coupled together using a wire. Direct couplingin this manner means that minimal or no resistive, inductive, orcapacitive isolation is used to achieve the combination of the I outputsignal 7511 with the Q output signal 7513.

This can be referred to as a wire-ored configuration (or a differentialwire-or configuration) because the I output 7511 and Q output 7513 aresimply connected together to form an IQ output 7514, without the needfor a summer. FIG. 76B illustrates the IQ output signal 7514 in the timedomain and illustrates the relative spacing of the I and Q portions ofthe IQ output signal 7514 in time. Since the I and Q portions of the IQ

output signal 7514 do not overlap, they can be directly combined atnodes 7518 a and 7518 b in a wired or configuration. The frequencydomain discussion of the IQ output signal 7514 is described furtherbelow.

Alternatively, in an embodiment, the I output signal 7511 and the Qoutput signal 7513 are coupled together indirectly through inductancesand/or capacitances that result in low or minimal impedance connections,and/or connections that result in minimal isolation and minimal powerloss. Alternatively, the I output signal 7511 and the Q output signal7513 are coupled using well known combining techniques, such asWilkinson, hybrid, transformers, or known active combiners.

The IQ output signal 7514 includes a plurality of harmonics, eachharmonic includes the baseband information of the baseband I signal 7502and the baseband Q signal 7504. It is noted that the quadraturerelationship between the I signal 7502 and the Q signal 7504 isimplemented using the control signals 7507 a and 7507 b.

FIG. 77A-C further illustrate the IQ output signal 7514. FIG. 77Adepicts an exemplary frequency spectrum for the I output signal 7511having harmonic images 7702 a-n. The images 7702 repeat at harmonics ofthe sampling frequency 1/T_(S), where each image 7702 contains thenecessary amplitude and frequency information to reconstruct the Ibaseband signal 7502. Likewise, FIG. 77B depicts an exemplary frequencyspectrum for the Q output signal 7513 having harmonic images 7704 a-n.The harmonic images 7704 a-n also repeat at harmonics of the samplingfrequency 1/T_(s), where each image 7704 contains the necessaryamplitude, frequency, and phase information to reconstruct the Qbaseband signal 7504.

FIG. 77C illustrates an exemplary frequency spectrum for the combinedharmonically rich signal 7514 having images 7706. Each image 7706carries the I baseband information and the Q baseband information fromthe corresponding images 7502 and 7504, respectively, withoutsubstantially increasing the frequency bandwidth occupied by eachharmonic 7706. This can occur because the Q output signal 7513 isshifted by 90 degrees relative to the I output signal 7511. The resultis that the images 7702 a-n and 7704 a-n effectively share the samesignal bandwidth due to their orthogonal relationship. For example, theimages 7702 a and 7704 a effectively share the frequency spectrum thatis represented by the image 7706 a. A filter can then be used to selectone of the harmonics 7706 a-n, as represented by the passband 7708. Theselected or filtered

signal 7708 can then be transmitted over a transmission medium, such asa wireless or wired medium.

The relative amplitude of the frequency images 7706 is generally afunction of the harmonic number and the pulse width T_(A). As such, therelative amplitude of a particular harmonic 7706 can be increased (ordecreased) by adjusting the pulse width T_(A) of the control signals7507 a and 7507 b. In general, shorter pulse widths of T_(A) shift moreenergy into the higher frequency harmonics, and longer pulse widths ofT_(A) shift more energy into the lower frequency harmonics.Additionally, the relative amplitude of a particular harmonic 7706 canalso be adjusted by adding/tuning an optional impedance (not shown)across the output resistor 7512.

FIGS. 77D-77G further describe the output spectrums and energydistribution that is available for the plurality of harmonic images,based on the aperture size of the control signal 7507. For example,FIGS. 77D and 77F illustrate a square wave as the control signal for thecontrol signal 7507, and the corresponding frequency spectrum thatresults for the harmonic images 7514. Specifically, the frequencyspectrum when a square wave is used for the control signal 7507 includesall odd harmonics, where the fundamental frequency f₁ has the highestamplitude, and therefore highest energy as shown. The remainingharmonics have increasingly lower energy.

In comparison, FIGS. 77F-77G illustrate the frequency spectrum ofharmonic images that are produced using an aperture or pulsewidthT_(A)=T₂ for the control signal 7507. Referring to FIG. 77F, the controlsignal has a first period T₁ (1/f₁) that represents the time-spacingbetween the pulses, where each pulse has a pulsewidth T₂ (1/f₂). Thementioned control signal produces a spectrum having plurality ofharmonics as shown in FIG. 77G. Referring to FIG. 77G, the energydistribution is such that the energy peaks at the harmonics f₁ and f₂.The pulsewidth T₂ of the control signal is chosen so as to improveenergy transfer into the frequency f₂. In other words, more energy canbe shifted into the harmonics (other than f₁) at the frequency f₂ bysimply adjusting the pulsewidth of the control signal 7507. Inembodiments, the pulsewidth T₂ is chosen to be approximately thehalf-sine of the frequency of interest.

FIG. 78 illustrates a flowchart 7800 that further describes theoperation of the IQ Differential Modulator 7500 according embodiments ofthe present invention. As discussed above, the IQ differential modulator7500 receives a differential in-phase signal

7502 and differential quadrature signal 7504, and up-converts thedifferential in-phase and quadrature signals 7502 and 7504 to generatean IQ output signal 7514 that is applied across the resistor 7512.

In step 7802, the IQ modulator 7500 receives I baseband signal 7502 andthe Q baseband signal 7504. Specifically, the impedances 7508 a and 7508b receive the I baseband signal 7502, and the impedance 7508 c and 7508d receive the Q baseband signal 7504.

In step 7804, the control signal generators 7506 a and 7506 b generatethe control signals 7507 a and 7507 b, respectively. The control signals7507 a and 7507 b have a plurality of pulses that are approximately 270degrees out-of-phase with respect to each other.

In step 7806, the FET device 7510 a shorts the differential componentsof the I baseband signal 7502 together according to the control signal7507 a to generate the I output signal 7511. The FET device 7510 bshorts the differential components of the Q baseband signal 7504together according to the control signal 7507 b to generate the Q outputsignal 7513.

In step 7808, the I output signal 7511 is combined with the Q outputsignal 7513 to form the IQ output signal 7514. The IQ output signal 7514includes a plurality of harmonics, each harmonic includes the basebandinformation of the baseband I signal 7502 and the baseband Q signal7504. It is noted that the quadrature relationship between the I signal7502 and the Q signal 7504 is implemented using the control signals 7507a and 7507 b.

FIG. 79 illustrates an IQ Modulator 7900 that is a single-ended versionof the IQ Differential Modulator 7500, according to embodiments of thepresent invention. The modulator 7900 receives a single-ended in-phasesignal 7902 and a single-ended quadrature signal 7904, and up-convertsthe in-phase and quadrature signals 7902 and 7904 to generate an IQoutput signal 7914 that is applied across the load 7512. The IQ outputsignal 7914 includes a plurality of harmonic images, where each harmonicimage contains the baseband information in the I baseband signal 7902and the Q baseband signal 7904. In other words, each harmonic image inthe IQ output signal 7514 contains the necessary amplitude, frequency,and phase information to reconstruct the I baseband signal 7502 and theQ baseband signal 7504. The invention is not limited to using a

resistor for the load 7512. Other types of loads could be used as willbe understood by those skilled in the arts, including reactive networks.

The single-ended IQ modulator 7900 operates similar to the IQdifferential modulator 7500 that was described herein, except that thechannel 7906 a and the Q channel 7906 b are configured in a single-endedconfiguration instead of a differential configuration. Accordingly, theFET device 7510 a shunts the I channel 7906 a to ground according thepulses of the control signal 7507 a, so as to generate the I outputsignal 7908, instead of shunting differential components together.Likewise, the FET device 7510 b shorts the Q channel 7906 b to groundaccording to the pulses of the control signal 7507 b to produce the Qoutput signal 7910. As discussed above, I output signal 7908 includes aplurality of up-converted harmonic images, where each harmonic imageincludes the baseband information in the baseband I signal 7902. The Qoutput signal 7910 includes a plurality of up-converted harmonic,images, where each harmonic image includes the baseband information inthe baseband Q signal 7904.

The I output signal 7908 and the Q output signal 7910 are combined atthe summing node 7916, to produce the IQ output signal 7914 that issingle-ended and referenced to ground. This can be referred to as awire-ored configuration because the I output 7908 and Q output 7910 aresimply connected together to form the IQ output 7916, without the needfor a summer. Accordingly, the connection 7916 can be other referred toas a wire-or connection 7916 because the I and Q channel outputs aresummed together without a summer or combiner.

FIG. 80 illustrates an IQ differential receiver 8000 according toembodiments of the present invention. The receiver 8000 receives adifferential RF input signal 8010 having quadrature basebandinformation, and down-converts the I and Q channels to generate adifferential in-phase baseband signal 8002 and a quadrature basebandsignal 8004. Alternatively, the down-converted signals 8002 and 8004could be down-converted to an IF frequency, instead of baseband.

The IQ differential receiver 8000 includes a differential I channel 8006and a differential Q channel 8008, that produce I and Q respectivebaseband outputs 8002 and 8004. The differential I channel 8006 includesimpedances 8009 a and 8009 b, the FET device 7510 a, and the controlsignal generator 7506 a. The FET device 7510 a is configured so that itssource and drain are connected across the outputs of the impedances

8009 a and 8009 b. The gate of the FET device 7510 a is driven by acontrol signal 7507 a from the control signal generator 7506 a.Likewise, the differential Q channel 8008 includes impedances 7508 c and7508 d, a FET device 7510 b, and a control signal generator 7506 b. TheFET device 7510 b is configured so that its source and drain areconnected across respective outputs of the impedances 8009 c and 8009 d.The gate of the FET device 7510 b is driven by a control signal 7507 bfrom the control signal generator 7506 b. In embodiments, the impedances8009 include a storage element, such as a series capacitor or acapacitor to ground.

The differential receiver 8000 operates similar to that of the IQdifferential modulator 7500. The RF input signal 8010 is down-convertedto I and Q baseband outputs, instead of I and Q baseband inputs beingup-converted to an RF output signal as discussed for FIG. 75. In the Ichannel 8006, the FET device 7510 a samples the output of the impedancedevice 8009 a according to the control signal 7507 a, thereby chargingand discharging the impedance device 8009 a according to the controlsignal 7507 a. Likewise, in the Q channel 8008, the FET device 7510 bsamples the output of the impedance device 8009 b according to thecontrol signal 7507 b, thereby charging and discharging the impedancedevice 8009 b according to the control signal 7507 b. As discussedabove, in an embodiment, the control signal 7507 b is approximately 270degrees out-of-phase with the control signal 7507 a, so that the Qinformation in the RF input signal 8010 can be distinguished from the Iinformation. As a result of the sampling function and the relativephasing of the control signals, the I baseband information in the RFsignal 8010 is down-converted to the I output signal 8002, and the Qbaseband information is down-converted to the Q baseband signal 8004.

FIG. 81 illustrates a flowchart 8100 that further describes theoperation of the differential IQ receiver 8000. As discussed above, theIQ differential receiver 8000 receives an RF input signal 8010 carryingI and Q information and down-converts and outputs an I baseband signal8002 and a Q baseband signal 8004.

In step 8102, the IQ receiver 8000 receives an RF signal 8010 thatcarries in-phase (I) baseband information and quadrature (Q) basebandinformation. Specifically, the impedances 7508 a-d receive the RF inputsignal 8010.

In step 8104, wire-or(s) 8014 a and 8014 b generate an I-channel inputsignal 8011 a and a Q channel input signal 8011 b from the differentialRF input signal 8010.

In step 8106, the control signal generators 7506 a and 7506 b generatethe control signals 7507 a and 7507 b, respectively. The control signals7507 a and 7507 b have a plurality of pulses, where the control signal7507 b has a plurality of pulses that are approximately 270 degreesout-of-phase with the pulses of control signal 7507 a. In embodiments,the pulsewidth T_(A) (also referred to as aperture width) of the controlsignals 7507 is chosen to be the half-sine of the frequency of interestin the RF input signal 8010. Whereas, the fundamental period T_(S) ofthe control signals can correspond to a sub-harmonic of the frequency ofinterest in RE input signal 8010.

In step 8108, the FET device 7510 a shorts together (or samples) thedifferential output measured across the impedances 8009 a and 8009 b(I-channel) according to the control signal 7507 a, so as to generatethe I baseband signal 8002. The FET device 7510 b shorts together (orsamples) the differential output across the impedances 8009 c and 8009 d(Q-channel) according to the control signal 7507 b, so as to generatethe Q baseband signal 8004.

The IQ differential transmitter of FIG. 75 can be combined with the IQreceiver of FIG. 80 to create an IQ transceiver according to embodimentsof the invention. A hybrid can be used to combine the two components, aswill be understood by those skilled in the arts. The TQ transceiver canboth transmit and receive IQ signals in an efficient manner inaccordance with the description above.

7.3 Universal Transmitter and CDMA

The universal transmitter 2920 (FIG. 29) and the universal transmitter5700 (FIG. 57) can be used to up-convert every known useful analog anddigital baseband waveform including but not limited to: AM, FM, PM,BPSK, QPSK, MSK, QAM, ODFM, multi-tone, and spread spectrum signals. Forfurther illustration, FIG. 34A and FIG. 34B depict transmitter 2920configured to up-convert the mentioned modulation waveforms. FIG. 34Aillustrates transmitter 2920 configured to up-convert non-complexwaveform including AM and shaped BPSK. In FIG. 34A, these non-complex(and non-IQ) waveforms are received on the I terminal 3402, and the Qinput 3404 is grounded since only a single channel is needed. FIG. 34Billustrates a transmitter 2920 that is configured to receive both I andQ inputs for the up-conversion of complex waveforms including

QPSK, QAM, OFDM, GSM, and spread spectrum waveforms (including CDMA andfrequency hopping). The transmitters in FIGS. 34A and 34B are presentedfor illustrative purposes, and are not limiting. Other embodiments arepossible, as will be appreciated in view of the teachings herein.

CDMA is an input waveform that is of particular interest forcommunications applications. CDMA is the fastest growing digitalcellular communications standard in many regions, and now is widelyaccepted as the foundation for the competing third generation (3G)wireless standard. CDMA is considered to be the among the most demandingof the current digital cellular standards in terms of RF performancerequirements.

7.3.1 1S-95 CDMA Specifications

FIG. 35A and FIG. 35B illustrate the CDMA specifications for basestation and mobile transmitters as required by the IS-95 standard. FIG.35A illustrates a base station CDMA signal 3502 having a main lobe 3504and sidelobes 3506 a and 3506 b. For base station transmissions, IS-95requires that the sidelobes 3506 a,b are at least 45 dB below themainlobe 3504 (or 45 dbc) at an offset frequency of 750 kHz, and 60 dBcat an offset frequency of 1.98 MHZ. FIG. 35B illustrates similarrequirements for a mobile CDMA signal 3508 having a main lobe 3510 andsidelobes 3512 a and 3512 b. For mobile transmissions, CDMA requiresthat the sidelobes 3512 a,b are at least 42 dBc at a frequency offset of885 kHz, and 54 dBc at a frequency offset 1.98 MHZ.

Rho is another well known performance parameter for CDMA. Rho is afigure-of-merit that measures the amplitude and phase distortion of aCDMA signal that has been processed in some manner (e.g. amplified,up-converted, filtered, etc.) The maximum theoretical value for Rho is1.0, which indicates no distortion during the processing of the CDMAsignal. The IS-95 requirement for the baseband-to-RF interface isRho=0.9912. As will be shown by the test results below, the transmitter2920 (in FIG. 29) can up-convert a CDMA baseband signal and achieve Rhovalues of approximately Rho−0.9967. Furthermore, the modulator 2910 inthe transmitter 2920 achieves these results in standard CMOS (althoughthe invention is not limited to this example implementation), withoutdoing multiple up-conversions and IF filtering that is associated withconventional super-heterodyne configurations.

7.3.2 Conventional CDMA Transmitter

Before describing the CDMA implementation of transmitter 2920, it isuseful to describe a conventional super-heterodyne approach that is usedto meet the IS-95 specifications. FIG. 36 illustrates a conventionalCDMA transmitter 3600 that up-converts an input signal 3602 to an outputCDMA signal 3634. The conventional CDMA transmitter 3600 includes: abaseband processor 3604, a baseband filter 3608, a first mixer 3612, anamplifier 3616, a SAW filter 3620, a second mixer 3624, a poweramplifier 3628, and a band-select filter 3632. The conventional CDMAtransmitter operates as follows.

The baseband processor 3604 spreads the input signal 3602 with I and Qspreading codes to generate I signal 3606 a and Q signal 3606 b, whichare consistent with CDMA IS-95 standards. The baseband filter 3608filters the signals 3606 with the aim of reducing the sidelobes so as tomeet the sidelobe specifications that were discussed in FIGS. 35A and35B. Mixer 3612 up-converts the signal 3610 using a first LO signal 3613to generate an IF signal 3614. IF amplifier 3616 amplifies the IF signal3614 to generate IF signal 3618. SAW filter 3620 has a bandpass responsethat filters the IF signal 3618 to suppress any sidelobes caused by thenon-linear operations of the mixer 3614. As is understood by thoseskilled in the arts, SAW filters provide significant signal suppressionoutside the passband, but are relatively expensive and large compared toother transmitter components. Furthermore, SAW filters are typicallybuilt on specialized materials that cannot be integrated onto a standardCMOS chip with other components. Mixer 3624 up-converts the signal 3622using a second LO signal 3625 to generate RF signal 3626. Poweramplifier 3628 amplifies RF signal 3626 to generate signal 3630.Band-select filter 3632 bandpass filters RF signal 3630 to suppress anyunwanted harmonics in output signal 3634.

It is noted that transmitter 3602 up-converts the input signal 3602using an IF chain 3636 that includes the first mixer 3612, the amplifier3616, the SAW filter 3620, and the second mixer 3624. The IF chain 3636up-converts the input signal to an IF frequency and does IFamplification and SAW filtering in order to meet the IS-95 sidelobe andfigure-of-merit specifications. This is done because conventional wisdom

teaches that a CDMA baseband signal cannot be up-converted directly frombaseband to RF, and still meet the IS-95 linearity requirements.

7.3.3 CDMA Transmitter Using the Present Invention

For comparison, FIG. 37A illustrates an example CDMA transmitter 3700according to embodiments of the present invention. The CDMA transmitter3700 includes (it is noted that the invention is not limited to thisexample): the baseband processor 3604; the baseband filter 3608; the IQmodulator 2910 (from FIG. 29), the control signal generator 2642, thesub-harmonic oscillator 2646, the power amplifier 3628, and the filter3632. In the example of FIG. 37A, the baseband processor 3604, basebandfilter 3608, amplifier 3628, and the band-select filter 3632 are thesame as that used in the conventional transmitter 3602 in FIG. 36. Thedifference is that the IQ modulator 2910 in transmitter 3700 completelyreplaces the IF chain 3636 in the conventional transmitter 3602. This ispossible because the modulator 2910 up-converts a CDMA signal directlyfrom baseband-to-RF without any IF processing. The detailed operation ofthe CDMA transmitter 3700 is described with reference to the flowchart7300 (FIG. 73) as follows.

In step 7302, the input baseband signal 3702 is received.

In step 7304, the CDMA baseband processor 3604 receives the input signal3702 and spreads the input signal 3702 using I and Q spreading codes, togenerate an I signal 3704 a and a Q signal 3704 b. As will beunderstood, the I spreading code and Q spreading codes can be differentto improve isolation between the I and Q channels.

In step 7306, the baseband filter 3608 bandpass filters the I signal3704 a and the Q signal 3704 b to generate filtered I signal 3706 a andfiltered Q signal 3706 b. As mentioned above, baseband filtering is doneto improve sidelobe suppression in the CDMA output signal.

FIGS. 37B-37D illustrate the effect of the baseband filter 3608 on the Ian Q inputs signals. FIG. 37B depicts multiple signal traces (over time)for the filtered I signal 3706 a, and FIG. 37C depicts multiple signalt⁻ aces for the filtered Q signal 3706 b. As shown, the signals 3706 a,bcan be described as having an “eyelid” shape having a thickness 3715.The thickness 3715 reflects the steepness of passband roll off of thebaseband filter 3608. In other words, a relatively thick eyelid in thetime domain reflects a steep passband roll off in the frequency domain,and results in lower sidelobes for the output CDMA signal. However,there is a tradeoff, because as the eyelids become

thicker, then there is a higher probability that channel noise willcause a logic error during decoding at the receiver. The voltage rails3714 represent the +1/−1 logic states for the I and Q signals 3706, andcorrespond to the logic states in complex signal space that are shown inFIG. 37D.

In step 7308, the IQ modulator 2910 samples I and Q input signals 3706A,3706B in a differential and balanced fashion according to sub-harmonicclock signals 2623 and 2627, to generate a harmonically rich signal3708. FIG. 37E illustrates the harmonically rich signal 3708 thatincludes multiple harmonic images 3716 a-n that repeat at harmonics ofthe sampling frequency 1/T_(S). Each image 3716 a-n is a spread spectrumsignal that contains the necessary amplitude, frequency, and phaseinformation to reconstruct the input baseband signal 3702.

In step 7310, the amplifier 3628 amplifies the harmonically rich signal3708 to generate an amplified harmonically rich signal 3710.

Finally, the band-select filter 3632 selects the harmonic of interestfrom signal 3710, to generate an CDMA output signal 3712 that meetsIS-95 CDMA specifications.

This is represented by passband 3718 selecting harmonic image 3716 b inFIG. 37E.

An advantage of the CDMA transmitter 3700 is in that the modulator 2910up-converts a CDMA input signal directly from baseband to RF without anyIF processing, and still meets the IS-95 sidelobe and figure-of-meritspecifications. In other words, the modulator 2910 is sufficientlylinear and efficient during the up-conversion process that no IFfiltering or amplification is required to meet the IS-95 requirements.Therefore, the entire IF chain 3636 can be replaced by the modulator2910, including the expensive SAW filter 3620. Since the SAW filter iseliminated, substantial portions of the transmitter 3702 can beintegrated onto a single CMOS chip, for example, that uses standard CMOSprocess. More specifically, and for illustrative purposes only, thebaseband processor 3604, the baseband filter 3608, the modulator 2910,the oscillator 2646, and the control signal generator 2642 can beintegrated on a single CMOS chip, as illustrated by CMOS chip 3802 inFIG. 38, although the invention is not limited to this implementationexample.

FIG. 37F illustrates a transmitter 3720 that is similar to transmitter3700 (FIG. 37A) except that modulator 5701 replaces the modulator 2910.Transmitter 3700 operates similar to the transmitter 3700 and has allthe same advantages of the transmitter 3700.

Other embodiments discussed or suggested herein can be used to implementother CDMA transmitters according to the invention.

7.3.4 CDMA Transmitter Measured Test Results

As discussed above, the UFT-based modulator 2910 directly up-convertsbaseband CDMA signals to RF without any IF filtering, while maintainingthe required figures-of-merit for IS-95. The modulator 2910 has beenextensively tested in order to specifically determine the performanceparameters when up-converting CDMA signals. The test system andmeasurement results are discussed as follows.

FIG. 39 illustrates a test system 3900 that measures the performance ofthe modulator 2910 when up-converting CDMA baseband signals. The testsystem 3900 includes: a Hewlett Packerd (HP) generator E4433B,attenuators 3902 a and 3902 b, control signal generator 2642, UFT-basedmodulator 2910, amplifier/filter module 3904, cable/attenuator 3906, andHP 4406A test set. The HP generator E4433B generates I and Q CDMAbaseband waveforms that meet the IS-95 test specifications. Thewaveforms are routed to the UFT-based modulator 2910 through the 8-dBattenuators 3902 a and 3902 b. The HP generator E4433B also generatesthe sub-harmonic clock signal 2645 that triggers the control signalgenerator 2642, where the sub-harmonic clock 2645 has a frequency of 279MHZ. The modulator 2910 up-converts the I and Q baseband signals togenerate a harmonic rich signal 3903 having multiple harmonic imagesthat represent the input baseband signal and repeat at the samplingfrequency. The amplifier/filter module 3904 selects and amplifies the3rd harmonic (of the 279 MHZ clock signal) in the signal 3903 togenerate the signal 3905 at 837 MHZ. The HP 4406A test set accepts thesignal 3905 for analysis through the cable/attenuator 3906. The HP 4406Ameasures CDMA modulation attributes including: Rho, EVM, phase error,amplitude error, output power, carrier insertion, and ACPR. In addition,the signal is demodulated and Walsh code correlation parameters areanalyzed. Both forward and reverse links have been characterized usingpilot, access, and traffic channels. For further illustration, FIG.4060Z display the measurement results for the RF spectrum 3905 based onvarious base station and mobile waveforms that are generated by the HPE443B generator.

FIGS. 40 and 41 summarize the performance parameters of the modulator2910 as measured by the test set 3900 for base station and mobilestation input waveforms, respectively. For the base station, table 4002includes lists performance parameters that

were measured at a base station middle frequency and includes: Rho, EVM,phase error, magnitude error, carrier insertion, and output power. It isnoted that Rho=0.997 for the base station middle frequency and exceedsthe IS-95 requirement of Rho−0.912. For the mobile station, FIG. 41illustrates a table 4102 that lists performance parameters that weremeasured at low, middle, and high frequencies. It is noted that the Rhoexceeds the IS-95 requirement (0.912) for each of the low, middle, highfrequencies of the measured waveform.

FIG. 42 illustrates a base station constellation 4202 measured during apilot channel test. A signal constellation plots the various logiccombinations for the I and Q signals in complex signal space, and is theraw data for determining the performance parameters (including Rho) thatare listed in Table 40. The performance parameters (in table 40) arealso indicated beside the constellation measurement 4202 forconvenience. Again, it is noted that Rho=0.997 for this test. A value of1 is perfect, and 0.912 is required by the IS-95 CDMA specification,although most manufactures strive for values greater than 0.94. This isa remarkable result since the modulator 2910 up-converts directly frombaseband-to-RF without any IF filtering.

FIG. 43 illustrates a base station sampled constellation 4302, anddepicts the tight constellation samples that are associated with FIG.42. The symmetry and sample scatter compactness are illustrative of thesuperior performance of the modulator 2910.

FIG. 44 illustrates a mobile station constellation 4402 measured duringan access channel test. As shown, Rho=0.997 for the mobile stationwaveforms. Therefore, the modulator 2910 operates very well withconventional and offset shaped QPSK modulation schemes.

FIG. 45 illustrates a mobile station sampled constellation 4502.Constellation 4502 illustrates excellent symmetry for the constellationsample scatter diagram.

FIG. 46 illustrates a base station constellation 4602 using only the HPtest equipment. The modulator 2910 has been removed so that the basestation signal travels only through the cables that connect the HPsignal generator E4433B to the HP 4406A test set. Therefore,constellation 4602 measures signal distortion caused by the test setcomponents (including the cables and the attenuators). It is noted thatRho=0.9994 for this measurement using base station waveforms. Therefore,at least part of the minimal

signal distortion that is indicated in FIGS. 42 and 43 is caused by thetest set components, as would be expected by those skilled in therelevant arts.

FIG. 47 illustrates a mobile station constellation 4702 using only theHP test equipment. As in FIG. 46, the modulator 2910 has been removed sothat the mobile station signal travels only through the cables thatconnect the HP signal generator E4433B to the HP 4406A test set.Therefore, constellation 4602 measures signal distortion caused by thetest set components (including the cables and the attenuators). It isnoted that Rho=0.9991 for this measurement using mobile stationwaveforms. Therefore, at least part of the signal distortion indicatedin FIGS. 44 and 45 is caused by the test set components, as would beexpected.

FIG. 48 illustrates a frequency spectrum 4802 of the signal 3905 with abase station input waveform. The frequency spectrum 4802 has a main lobeand two sidelobes, as expected for a CDMA spread spectrum signal. Theadjacent channel power ratio (ACPR) measures the spectral energy at aparticular frequency of the side lobes relative to the main lobe. Asshown, the frequency spectrum 4802 has an ACPR=−48.34 dBc and −62.18 dBcat offset frequencies of 750 KHz and 1.98 MHZ, respectively. The IS-95ACPR requirement for a base station waveform is −45 dBc and −60 dBcmaximum, at the offset frequencies of 750 kHz and 1.98 MHZ,respectively. Therefore, the modulator 2910 has more than 3 dB and 2 dBof margin over the IS-95 requirements for the 750 kHz and 1.98 MHZoffsets, respectively.

FIG. 49 illustrates a histogram 4902 that corresponds to the spectrumplot in FIG. 48. The histogram 4902 illustrates the distribution of thespectral energy in the signal 3905 for a base station waveform.

FIG. 50 illustrates a frequency spectrum 5002 of the signal 3905 with amobile station input waveform. As shown, the ACPR measurement is −52.62dBc and −60.96 dBc for frequency offsets of 885 kHz and 1.98 MHZ,respectively. The IS-95 ACPR requirement for a mobile station waveformis approximately −42 dBc and −54 dBc, respectively. Therefore, themodulator 2910 has over 10 dB and 6 dB of margin above the IS-95requirements for the 885 kHz and 1.98 MHZ frequency offsets,respectively.

FIG. 51 illustrates a histogram 5102 that corresponds to the mobilestation spectrum plot in FIG. 50. The histogram 5102 illustrates thedistribution of the spectral energy in the signal 3905 for a mobilestation waveform.

FIG. 52A illustrates a histogram 5202 for crosstalk vs. CDMA channelwith a base station input waveform. More specifically, the HP E4406A wasutilized as a receiver to analyze the orthogonality of codessuperimposed on the base station modulated spectrum. The HP E4406Ademodulated the signal provided by the modulator/transmitter anddetermined the crosstalk to non-active CDMA channels. The pilot channelis in slot ‘0’ and is the active code for this test. All non-activecodes are suppressed in the demodulation process by greater than 40 dB.The IS-95 requirement is 27 dB of suppression so that there is over 13dB of margin. This implies that the modulator 2910 has excellent phaseand amplitude linearity.

In additions to the measurements described above, measurements were alsoconducted to obtain the timing and phase delays associated with a basestation transmit signal composed of pilot and active channels. Deltameasurements were extracted with the pilot signal as a reference. Thedelay and phase are −5.7 ns (absolute) and 7.5 milli radians, worstcase. The standard requires less than 50 ns (absolute) and 50 milliradians, which the modulator 2910 exceeded with a large margin.

The performance sensitivity of modulator 2910 was also measured overmultiple parameter variations. More specifically, the performancesensitivity was measured vs. IQ input signal level variation and LOsignal level variation, for both base station and mobile stationmodulation schemes. (LO signal level is the signal level of thesubharmonic clock 2645 in FIG. 39.) FIGS. 52B-0 depict performancesensitivity of the modulator 2910 using the base station modulationscheme, and FIGS. 52P-Z depict performance sensitivity using the mobilestation modulation scheme. These plots reveal that the modulator 2910 isexpected to enable good production yields since there is a largeacceptable operating performance range for I/Q and LO peak to peakvoltage inputs. The plots are described further as follows.

FIG. 52B illustrates Rho vs. shaped IQ input signal level using basestation modulation.

FIG. 52C illustrates transmitted channel power vs. shaped IQ inputsignal level using base station modulation.

FIG. 52D illustrates ACPR vs. shaped IQ Input signal level using basestation modulation.

FIG. 52E illustrates EVM and Magnitude error vs shaped IQ input levelusing base station modulation.

FIG. 52F illustrates carrier feed thru vs. shaped IQ input signal levelusing base station modulation.

FIG. 52G illustrates Rho vs. LO signal level using base stationmodulation.

FIG. 52H illustrates transmitted channel power vs. LO signal level usingbase station modulation.

FIG. 521 illustrates ACPR vs. LO signal level using base stationmodulation.

FIG. 52J illustrates EVM and magnitude error vs LO signal level usingbase station modulation.

FIG. 52K illustrates carrier feed thru vs. LO signal level using basestation modulation.

FIG. 52L illustrates carrier feed thru vs IQ input level over a widerange using base station modulation.

FIG. 52M illustrates ACPR vs. shaped IQ input signal level using basestation modulation.

FIG. 52N illustrates Rho vs. shaped IQ input signal level using basestation modulation.

FIG. 520 illustrates EVM, magnitude error, and phase error vs. shaped IQinput signal level using base station modulation.

FIG. 52P illustrates Rho vs. shaped IQ input signal level using mobilestation modulation.

FIG. 52Q illustrates transmitted channel power vs. shaped IQ inputsignal level using mobile station modulation.

FIG. 52R illustrates ACPR vs. shaped IQ Input signal level using mobilestation modulation.

FIG. 52S illustrates EVM, magnitude error, and phase error vs. shaped IQinput level using mobile station modulation.

FIG. 52T illustrates carrier feed thru vs. shaped I Q input signal levelusing mobile station modulation.

FIG. 52U illustrates Rho vs. LO signal level using mobile stationmodulation.

FIG. 52V illustrates transmitted channel power vs. LO signal level usingmobile station modulation.

FIG. 52W illustrates ACPR vs. LO signal level using mobile stationmodulation.

FIG. 52X illustrates EVM and magnitude error vs. LO signal level usingmobile station modulation.

FIG. 52Y illustrates carrier feed thru vs. LO signal level using mobilestation modulation.

FIG. 52Z illustrates an approximate power budget for a CDMA modulatorbased on the modulator 2910.

FIGS. 52B-Z illustrate that the UFT-based complex modulator 2910comfortably exceeds the IS-95 transmitter performance requirements forboth mobile and base station modulations, even with signal levelvariations. Testing indicates that Rho as well as carrier feed throughand ACPR are not overly sensitive to variations in I/Q levels and LOlevels. Estimated power consumption for the modulator 2910 is lower thanequivalent two-state superheterodyne architecture. This means that apractical UFT based CDMA transmitter can be implemented in bulk CMOS andefficiently produced in volume.

The UFT architecture achieves the highest linearity per milliwatt ofpower consumed of any radio technology of which the inventors are aware.This efficiency comes without a performance penalty, and due to theinherent linearity of the UFT technology, several important performanceparameters may actually be improved when compared to traditionaltransmitter techniques.

Since the UFT technology can be implemented in standard CMOS, new systempartitioning options are available that have not existed before. As anexample, since the entire UFT-based modulator can be implemented inCMOS, it is plausible that the modulator and other transmitter functionscan be integrated with the digital baseband processor leaving only a fewexternal components such as the final bandpass filter and the poweramplifier. In addition to the UFT delivering the required linearity anddynamic range performance, the technology also has a high level ofimmunity to digital noise that would be found on the same substrate whenintegrated with other digital circuitry. This is a significant steptowards enabling a complete wireless system-on-chip solution.

It is noted that the test setup, procedures, and results discussed aboveand shown in the figures were provided for illustrative purposes only,and do not limit the invention to any particular embodiment,implementation or application.

8. Integrated Up-Conversion and Spreading of a Baseband Signal

Previous sections focused on up-converting a spread spectrum signaldirectly from baseband-to-RF, without preforming any IF processing. Inthese embodiments, the baseband signal was already a spread spectrumsignal prior to up-conversion. The following discussion focuses onembodiments that perform the spreading function and the frequencytranslation function in a simultaneously and in an integrated manner.One type of spreading code is Code Division Multiple Access (or CDMA),although the invention is not limited to this. The present invention canbe implemented in CDMA, and other spread spectrum systems as will beunderstood by those skilled in the arts based on the teachings herein.

8.1 Integrated Up-Conversion and Spreading Using an Amplitude Shaper

FIG. 53A illustrates a spread spectrum transmitter 5300 that is based onthe UFT-based modulator 2604 that was discussed in FIG. 26A. Spreadspectrum transmitter 5300 performs simultaneous up-conversion andspreading of an input baseband signal 5302 to generate an output signal5324. As will shown, the spreading is accomplished by placing thespreading code on the control signals that operate the UFT modules inthe modulator 2604 so that the spreading and up-conversion areaccomplished in an integrated manner. In order to limit sidelobespectral growth in the output signal 5324, the amplitude of the inputbaseband signal 5302 is shaped so as to correspond with the spreadingcode. The operation of spread spectrum transmitter 5300 is described indetail as follows with reference to flowchart 6700 that is shown in FIG.67. The order of the steps in flowchart 6700 are not limiting and may bere-arranged as will be understood by those skilled in the arts. (This isgenerally true of all flowcharts discussed herein).

In step 6701, the spread spectrum transmitter 5300 receives the inputbaseband signal 5302.

In step 6702, the oscillator 2646 generates the clock signal 2645. Asdescribed earlier, the clock signal 2645 is in embodiments asub-harmonic of the output signal 5324. Furthermore, in embodiments ofthe invention, the clock signal 2645 is a periodic square wave orsinusoidal clock signal.

In step 6704, a spreading code generator 5314 generates a spreading code5316. In embodiments of the invention, the spreading code 5316 is a PNcode, or any other type of spreading code that is useful for generatingspread spectrum signals.

In step 6706, the multiplier 5318 modulates the clock signal 2645 withthe spreading code 5316 to generate spread clock signal 5320. As such,the spread clock signal 5320 carries the spreading code 5316.

In step 6708, the control signal generator 2642 receives the spreadclock signal 5320, and generates control signals 5321 and 5322 thatoperate the UFT modules in the modulator 2604. The control signals 5321and 5322 are similar to clock signals 2623 and 2627 that were discussedin FIG. 26. In other words, the clock signals 5321 and 5322 include aplurality of pulses having a pulse width TA that is established toimprove energy transfer to a desired harmonic in the resultingharmonically rich signal. Additionally, the control signals 5321 and5322 are phase shifted with respect to each other by approximately 180degrees (although the invention is not limited to this example), as werethe control signals 2623 and 2627. However, the control signals 5321 and5322 are modulated with (and carry) the spreading code 5316 because theywere generated from spread clock signal 5320.

In step 6710, the amplitude shaper 5304 receives the input basebandsignal 5302 and shapes the amplitude so that it corresponds with thespreading code 5316 that is generated by the code generator 5314,resulting in a shaped input signal 5306. This is achieved by feeding thespreading code 5316 back to the amplitude shaper 5304 and smoothing theamplitude of the input baseband signal 5302, accordingly.

FIG. 53B illustrates the resulting shaped input signal 5306 and thecorresponding spreading code 5316. The amplitude of the input signal5302 is shaped such that it is smooth and so that it has zero crossingsthat are in time synchronization with the spreading code 5316. Bysmoothing input signal amplitude, high frequency components are removedfrom the input signal prior to sampling, which results lower sidelobeenergy in the harmonic images produced during sampling. Implementationof amplitude shaper 5304 will be apparent to persons skilled in the artbase on the functional teachings combined herein.

In step 6712, the low pass filter 5308 filters the shaped input signal5306 to remove any unwanted high frequency components, resulting in afiltered signal 5310.

In step 6714, the modulator 2604 samples the signal 5310 in a balancedand differential manner according to the control signals 5320 and 5322,to generate a harmonically rich signal 5312. As discussed in referenceto FIG. 26, the control signals 5320 and 5322 trigger the controlledswitches in the modulator 2604, resulting in multiple harmonic images ofthe baseband signal 5302 in the harmonically rich signal 5312. Since thecontrol signals carry the spreading code 5316, the modulator 2604up-converts and spreads the filtered signal 5310 in an integrated mannerduring the sampling process. As such, the harmonic images in theharmonically rich signal 5312 are spread spectrum signals. FIG. 53Cillustrates the harmonically rich signal 5312 that includes multipleharmonic images 5320 a-n that repeat at harmonics of the samplingfrequency 1/T_(s). Each image 5320 a-n is a spread spectrum signal thatcontains the necessary amplitude and frequency information toreconstruct the input baseband signal 5302.

In step 6716, the optional filter 2606 selects a desired harmonic (orharmonics) from the harmonically rich signal 5312. This is presented bythe passband 5322 selecting the spread harmonic 5320 c in FIG. 53C.

In step 6718, the optional amplifier 2608 amplifies the desired harmonic(or harmonics) for transmission.

As mentioned above, an advantage of the spread spectrum transmitter 5300is that the spreading and up-conversion is accomplished in asimultaneous and integrated manner. This is a result of modulating thecontrol signals that operate the UFT modules in the balanced modulator2604 with the spreading code prior to sampling of the baseband signal.Furthermore, by shaping the amplitude of the baseband signal prior tosampling, the sidelobe energy in the spread spectrum harmonics isminimized. As discussed above, minimal sidelobe energy is desirable inorder to meet the sidelobe standards of the CDMA IS-95 standard (seeFIGS. 43A and 43B).

FIG. 61 illustrates an IQ spread spectrum modulator 6100 that is basedon the spread spectrum transmitter 5300. Spread spectrum modulator 6100performs simultaneous up-conversion and spreading of an I basebandsignal 6102 and a Q baseband signal 6118 to generate an output signal6116 that carries both the I and Q baseband information. The operationof the modulator 6100 is described in detail with reference to theflowchart 6800 that is shown in FIGS. 68A and 68B. The steps in

flowchart 6800 are not limiting and may be re-arranged as will beunderstood by those skilled in the arts.

In step 6801, the IQ modulator 6100 receives the I data signal 6102 andthe Q data signal 6118.

In step 6802, the oscillator 2646 generates the clock signal 2645. Asdescribed earlier, the clock signal 2645 is in embodiments asub-harmonic of the output signal 6116. Furthermore, in embodiments ofthe invention, the clock signal 2645 is a periodic square wave orsinusoidal clock signal.

In step 6804, an I spreading code generator 6140 generates an Ispreading code 6144 for the I channel. Likewise, a Q spreading codegenerator 6138 generates a Q spreading code 6142 for the Q channel. Inembodiments of the invention, the spreading codes are PN codes, or anyother type of spreading code that is useful for generating spreadspectrum signals. In embodiments of the invention, the I spreading codeand Q spreading code can be the same spreading code. Alternatively, theI and Q spreading codes can be different to improve isolation betweenthe I and Q channels, as will be understood by those skilled in thearts.

In step 6806, the multiplier 5318 a modulates the clock signal 2645 withthe I spreading code 6144 to generate a spread clock signal 6136.Likewise, the multiplier 5318 b modulates the clock signal 2645 with theQ spreading code 6142 to generate a spread clock signal 6134.

In step 6808, the control signal generator 2642 a receives the I clocksignal 6136 and generates control signals 6130 and 6132 that operate theUFT modules in the modulator 2604 a. The controls signals 6130 and 6132are similar to clock signals 2623 and 2627 that were discussed in FIG.26. The difference being that signals 6130 and 6132 are modulated with(and carry) the I spreading code 6144. Likewise, the control signalgenerator 2642 b receives the Q clock signal 6134 and generates controlsignals 6126 and 6128 that operate the UFT modules in the modulator 2604b. In step 6810, the amplitude shaper 5304 a receives the I data signal6102 and the shapes the amplitude so that it corresponds with thespreading code 6144, resulting in I shaped data signal 6104. This isachieved by feeding the spreading code 6144 back to the amplitude shaper5304 a. The amplitude shaper then shapes the amplitude of the inputbaseband signal 6102 to correspond to the spreading code 6144, asdescribed for spread spectrum transmitter

5300. More specifically, the amplitude of the input signal 6102 isshaped such that it is smooth and so that it has zero crossings that arein time synchronization with the I spreading code 6144. Likewise, theamplitude shaper 5304 h receives the Q data signal 6118 and shapesamplitude of the Q data signal 6118 so that it corresponds with the Qspreading code 6142, resulting in Q shaped data signal 6120.

In step 6812, the low pass filter 5308 a filters the I shaped datasignal 6104 to remove any unwanted high frequency components, resultingin a I filtered signal 6106. Likewise, the low pass filter 5308 bfilters the Q shaped data signal 6120, resulting in Q filtered signal6122.

In step 6814, the modulator 2604 a samples the I filtered signal 6106 ina balanced and differential manner according to the control signals 6130and 6132, to generate a harmonically rich signal 6108. As discussed inreference to FIG. 26, the control signals 6130 and 6132 trigger thecontrolled switches in the modulator 2604 a, resulting in multipleharmonic images in the harmonically rich signal 6108, where each imagecontains the I baseband information. Since the control signals 6130 and6132 also carry the I spreading code 6144, the modulator 2604 aup-converts and spreads the filtered signal 6106 in an integrated mannerduring the sampling process. As such, the harmonic images in theharmonically rich signal 6108 are spread spectrum signals.

In step 6816, the modulator 2604 b samples the Q filtered signal 6122 ina balanced and differential manner according to the control signals 6126and 6128, to generate a harmonically rich signal 6124. The controlsignals 6126 and 6128 trigger the controlled switches in the modulator2604 b, resulting in multiple harmonic images in the harmonically richsignal 6124, where each image contains the Q baseband information. Aswith modulator 2604 a, the control signals 6126 and 6128 carry the Qspreading code 6142 so that the modulator 2604 b up-converts and spreadsthe filtered signal 6122 in an integrated manner during the samplingprocess. In other words, the harmonic images in the harmonically richsignal 6124 are also spread spectrum signals.

In step 6818, a 90 signal combiner 6146 combines the I harmonically richsignal 6108 and the Q harmonically rich signal 6124, to generate the IQharmonically rich signal 6148. The IQ harmonically rich signal 6148contains multiple harmonic images, where each images contains the spreadI data and the spread Q data. The 90 degree combiner

phase shifts the Q signal 6124 relative to the I signal 6108 so that noincrease in spectrum width is needed for the IQ signal 6148, whencompared the I signal or the Q

In step 6820, the optional bandpass filter 2606 select the harmonic (orharmonics) of interest from the harmonically rich signal 6148, togenerate signal 6114.

In step 6222, the optional amplifier 2608 amplifies the desired harmonic6114 for transmission.

8.2 Integrated Up-Conversion and Spreading Using a Smoothing VaryingClock Signal

FIG. 54A illustrates a spread spectrum transmitter 5400 that is a secondembodiment of balanced UFT modules that perform up-conversion andspreading simultaneously. More specifically, the spread spectrumtransmitter 5400 does simultaneous up-conversion and spreading of an Idata signal 5402 a and a Q data signal 5402 b to generate an IQ outputsignal 5428. Similar to modulator 6100, transmitter 5400 modulates theclock signal that controls the UFT modules with the spreading codes tospread the input I and Q signals during up-conversion. However, thetransmitter 5400 modulates the clock signal by smoothly varying theinstantaneous frequency or phase of a voltage controlled oscillator(VCO) with the spreading code. The transmitter 5400 is described indetail as follows with reference to a flowchart 6900 that is shown inFIGS. 69A and 69B.

In step 6901, the transmitter 5400 receives the I baseband signal 5402 aand the Q baseband signal 5402 b.

In step 6902, a code generator 5423 generates a spreading code 5422. Inembodiments of the invention, the spreading code 5422 is a PN code orany other type off useful code for spread spectrum systems.Additionally, in embodiments of the invention, there are separatespreading codes for the I and Q channels.

In step 6904, a clock driver circuit 5421 generates a clock driversignal 5420 that is phase modulated according to a spreading code 5422.FIG. 54B illustrates the clock driver signal 5420 as series of pulses,where the instantaneous frequency (or phase) of the pulses is determinedby the spreading code 5422, as shown. In embodiments of the

invention, the phase of the pulses in the clock driver 5420 is variedsmoothly in correlation with the spreading code 5422.

In step 6906, a voltage controlled oscillator 5418 generates a clocksignal 5419 that has a frequency that varies according to a clock driversignal 5420. As mentioned above, the phase of the pulses in the clockdriver 5420 is varied smoothly in correlation with the spreading code5422 in embodiments of the invention. Since the clock driver 5420controls the oscillator 5418, the frequency of the clock signal 5419varies smoothly as a function of the PN code 5422. By smoothly varyingthe frequency of the clock signal 5419, the sidelobe growth in thespread spectrum images is minimized during the sampling process.

In step 6908, the pulse generator 2644 generates a control signal 5415based on the clock signal 5419 that is similar to either one thecontrols signals 2623 or 2627 (in FIGS. 27A and 27B). The control signal5415 carries the spreading code 5422 via the clock signal 5419. Inembodiments of the invention, the pulse width (TA) of the control signal5415 is established to enhance or optimize energy transfer to specificharmonics in the harmonically rich signal 5428 at the output. For the Qchannel, a phase shifter 5414 shifts the phase of the control signal5415 by 90 degrees to implement the desired quadrature phase shiftbetween the I and Q channels, resulting in a control signal 5413.

In step 6910, a low pass filter (LPF) 5406 a filters the I data signal5402 a to remove any unwanted high frequency components, resulting in anI signal 5407 a. Likewise, a LPF 5406 b filters the Q data signal 5402 bto remove any unwanted high frequency components, to generate the Qsignal 5407 b.

In step 6912, a UFT module 5408 a samples the I data signal 5407 aaccording to the control signal 5415 to generate a harmonically richsignal 5409 a. The harmonically rich signal 5409 a contains multiplespread spectrum harmonic images that repeat at harmonics of the samplingfrequency. Similar to transmitter 5300, the harmonic images in signal5409 a carry the I baseband information, and are spread spectrum due tothe spreading code on the control signal 5415.

In step 6914, a UFT module 5408 b samples the Q data signal 5407 baccording to the control signal 5413 to generate harmonically richsignal 5409 b. The harmonically rich signal 5409 b contains multiplespread spectrum harmonic images that repeat at harmonics of the samplingfrequency. The harmonic images in signal 5409 a carry the Q baseband

information, and are spread spectrum due to the spreading code on thecontrol signal 5413.

In step 6916, a signal combiner 5410 combines the harmonically richsignal 5409 a with the harmonically rich signal 5409 b to generate an IQharmonically rich signal 5412. The harmonically rich signal 5412 carriesmultiple harmonic images, where each image carries the spread I data andthe spread Q data.

In step 6918, the optional bandpass filter 5424 selects a harmonic (orharmonics) of interest for transmission, to generate the IQ outputsignal 5428.

FIG. 54C illustrates a transmitter 5430 that is similar to thetransmitter 5400 except that the UFT modules are replaced by balancedUFT modulators 2604 that were described in FIG. 26. Also, the pulsegenerator is replaced by the control signal generator 2642 to generatethe necessary control signals to operate the UFT modules in the balancedmodulators. By replacing the UFT modules with balanced UFT modulators,sidelobe suppression can be improved.

9. Shunt Receiver Embodiments Utilizing UFT Modules

In this section, example receiver embodiments are presented that utilizeUFT modules in a differential and shunt configuration. Morespecifically, embodiments, according to the present invention, areprovided for reducing or eliminating DC offset and/or reducing oreliminating circuit re-radiation in receivers, including I/Q modulationreceivers and other modulation scheme receivers. These embodiments aredescribed herein for purposes of illustration, and not limitation. Theinvention is not limited to these embodiments. Alternate embodiments(including equivalents, extensions, variations, deviations, etc., of theembodiments described herein) will be apparent to persons skilled in therelevant art(s) based on the teachings contained herein. The inventionis intended and adapted to include such alternate embodiments.

9.1 Example I/Q Modulation Receiver Embodiments

FIGS. 70A1 and 70A2 illustrate an exemplary I/Q modulation receiver7000, according to an embodiment of the present invention. I/Qmodulation receiver 7000 has additional advantages of reducing oreliminating unwanted DC offsets and circuit re-radiation.

I/Q modulation receiver 7000 comprises a first UFD module 7002, a firstoptional filter 7004, a second UFD module 7006, a second optional filter7008, a third UFD module 7010, a third optional filter 7012, a fourthUFD module 7014, a fourth filter 7016, an optional LNA 7018, a firstdifferential amplifier 7020, a second differential amplifier 7022, andan antenna 7072.

I/Q modulation receiver 7000 receives, down-converts, and demodulates aI/Q modulated RF input signal 7082 to an 1 baseband output signal 7084,and a Q baseband output signal 7086. I/Q modulated RF input signal 7082comprises a first information signal and a second information signalthat are I/Q modulated onto an RF carrier signal. I baseband outputsignal 7084 comprises the first baseband information signal. Q basebandoutput signal 7086 comprises the second baseband information signal.

Antenna 7072 receives I/Q modulated RF input signal 7082. I/Q modulatedRF input signal 7082 is output by antenna 7072 and received by optionalLNA 7018. When present, LNA 7018 amplifies I/Q modulated RF input signal7082, and outputs amplified I/Q signal 7088.

First UFD module 7002 receives amplified I/Q signal 7088. First UFDmodule 7002 down-converts the I-phase signal portion of amplified inputI/Q signal 7088 according to an I control signal 7090. First UFD module7002 outputs an I output signal 7098.

In an embodiment, first UFD module 7002 comprises a first storage module7024, a first UFT module 7026, and a first voltage reference 7028. In anembodiment, a switch contained within first UFT module 7026 opens andcloses as a function of I control signal 7090. As a result of theopening and closing of this switch, which respectively couples andde-couples first storage module 7024 to and from first voltage reference7028, a down-converted signal, referred to as I output signal 7098,results. First voltage reference 7028 may be any reference voltage, andis preferably ground. I output signal 7098 is stored by first storagemodule 7024.

In an embodiment, first storage module 7024 comprises a first capacitor7074. In addition to storing I output signal 7098, first capacitor 7074reduces or prevents a DC offset voltage resulting from charge injectionfrom appearing on I output signal 7098.

I output signal 7098 is received by optional first filter 7004. Whenpresent, first filter 7004 is in some embodiments a high pass filter toat least filter I output signal 7098

to remove any carrier signal “bleed through”. In a preferred embodiment,when present, first filter 7004 comprises a first resistor 7030, a firstfilter capacitor 7032, and a first filter voltage reference 7034.Preferably, first resistor 7030 is coupled between I output signal 7098and a filtered I output signal 7007, and first filter capacitor 7032 iscoupled between filtered I output signal 7007 and first filter voltagereference 7034. Alternately, first filter 7004 may comprise any otherapplicable filter configuration as would be understood by personsskilled in the relevant art(s). First filter 7004 outputs filtered Ioutput signal 7007.

Second UFD module 7006 receives amplified I/Q signal 7088. Second UFDmodule 7006 down-converts the inverted I-phase signal portion ofamplified input I/Q signal 7088 according to an inverted I controlsignal 7092. Second UFD module 7006 outputs an inverted I output signal7001.

In an embodiment, second UFD module 7006 comprises a second storagemodule 7036, a second UFT module 7038, and a second voltage reference7040. In an embodiment, a switch contained within second UFT module 7038opens and closes as a function of inverted I control signal 7092. As aresult of the opening and closing of this switch, which respectivelycouples and de-couples second storage module 7036 to and from secondvoltage reference 7040, a down-converted signal, referred to as invertedI output signal 7001, results. Second voltage reference 7040 may be anyreference voltage, and is preferably ground. Inverted I output signal7001 is stored by second storage module 7036.

In an embodiment, second storage module 7036 comprises a secondcapacitor 7076. In addition to storing inverted I output signal 7001,second capacitor 7076 reduces or prevents a DC offset voltage resultingfrom charge injection from appearing on inverted I output signal 7001.

Inverted I output signal 7001 is received by optional second filter7008. When present, second filter 7008 is a high pass filter to at leastfilter inverted I output signal 7001 to remove any carrier signal “bleedthrough”. In a preferred embodiment, when present, second filter 7008comprises a second resistor 7042, a second filter capacitor 7044, and asecond filter voltage reference 7046. Preferably, second resistor 7042is coupled between inverted I output signal 7001 and a filtered invertedI output signal 7009, and second filter capacitor 7044 is coupledbetween filtered inverted I output signal

7009 and second filter voltage reference 7046. Alternately, secondfilter 7008 may comprise any other applicable filter configuration aswould be understood by persons skilled in the relevant art(s). Secondfilter 7008 outputs filtered inverted I output signal 7009.

First differential amplifier 7020 receives filtered I output signal 7007at its non-inverting input and receives filtered inverted I outputsignal 7009 at its inverting input. First differential amplifier 7020subtracts filtered inverted I output signal 7009 from filtered I outputsignal 7007, amplifies the result, and outputs I baseband output signal7084. Because filtered inverted I output signal 7009 is substantiallyequal to an inverted version of filtered I output signal 7007, Ibaseband output signal 7084 is substantially equal to filtered I outputsignal 7009, with its amplitude doubled. Furthermore, filtered I outputsignal 7007 and filtered inverted I output signal 7009 may comprisesubstantially equal noise and DC offset contributions from priordown-conversion circuitry, including first UFD module 7002 and secondUFD module 7006, respectively. When first differential amplifier 7020subtracts filtered inverted I output signal 7009 from filtered I outputsignal 7007, these noise and DC offset contributions substantiallycancel each other.

Third UFD module 7010 receives amplified 1/Q signal 7088. Third UFDmodule 7010 down-converts the Q-phase signal portion of amplified inputI/Q signal 7088 according to an Q control signal 7094. Third UFD module7010 outputs an Q output signal 7003.

In an embodiment, third UFD module 7010 comprises a third storage module7048, a third UFT module 7050, and a third voltage reference 7052. In anembodiment, a switch contained within third UFT module 7050 opens andcloses as a function of Q control signal 7094. As a result of theopening and closing of this switch, which respectively couples andde-couples third storage module 7048 to and from third voltage reference7052, a down-converted signal, referred to as Q output signal 7003,results. Third voltage reference 7052 may be any reference voltage, andis preferably ground. Q output signal 7003 is stored by third storagemodule 7048.

In an embodiment, third storage module 7048 comprises a third capacitor7078. In addition to storing Q output signal 7003, third capacitor 7078reduces or prevents a DC offset voltage resulting from charge injectionfrom appearing on Q output signal 7003.

Q output signal 7003 is received by optional third filter 7012. Whenpresent, in an embodiment, third filter 7012 is a high pass filter to atleast filter Q output signal 7003 to remove any carrier signal “bleedthrough”. In an embodiment, when present, third filter 7012 comprises athird resistor 7054, a third filter capacitor 7056, and a third filtervoltage reference 7058. Preferably, third resistor 7054 is coupledbetween Q output signal 7003 and a filtered Q output signal 7011, andthird filter capacitor 7056 is coupled between filtered Q output signal7011 and third filter voltage reference 7058. Alternately, third filter7012 may comprise any other applicable filter configuration as would beunderstood by persons skilled in the relevant art(s). Third filter 7012outputs filtered Q output signal 7011.

Fourth UFD module 7014 receives amplified I/Q signal 7088. Fourth UFDmodule 7014 down-converts the inverted Q-phase signal portion ofamplified input I/Q signal 7088 according to an inverted Q controlsignal 7096. Fourth UFD module 7014 outputs an inverted Q output signal7005.

In an embodiment, fourth UFD module 7014 comprises a fourth storagemodule 7060, a fourth UFT module 7062, and a fourth voltage reference7064. In an embodiment, a switch contained within fourth UFT module 7062opens and closes as a function of inverted Q control signal 7096. As aresult of the opening and closing of this switch, which respectivelycouples and de-couples fourth storage module 7060 to and from fourthvoltage reference 7064, a down-converted signal, referred to as invertedQ output signal 7005, results. Fourth voltage reference 7064 may be anyreference voltage, and is preferably ground. Inverted Q output signal7005 is stored by fourth storage module 7060.

In an embodiment, fourth storage module 7060 comprises a fourthcapacitor 7080. In addition to storing inverted Q output signal 7005,fourth capacitor 7080 reduces or prevents a DC offset voltage resultingfrom charge injection from appearing on inverted Q output signal 7005.

Inverted Q output signal 7005 is received by optional fourth filter7016. When present, fourth filter 7016 is a high pass filter to at leastfilter inverted Q output signal 7005 to remove any carrier signal “bleedthrough”. In a preferred embodiment, when present, fourth filter 7016comprises a fourth resistor 7066, a fourth filter capacitor 7068, and afourth filter voltage reference 7070. Preferably, fourth resistor 7066is coupled

between inverted Q output signal 7005 and a filtered inverted Q outputsignal 7013, and fourth filter capacitor 7068 is coupled betweenfiltered inverted Q output signal 7013 and fourth filter voltagereference 7070. Alternately, fourth filter 7016 may comprise any otherapplicable filter configuration as would be understood by personsskilled in the relevant art(s). Fourth filter 7016 outputs filteredinverted Q output signal 7013.

Second differential amplifier 7022 receives filtered Q output signal7011 at its non-inverting input and receives filtered inverted Q outputsignal 7013 at its inverting input. Second differential amplifier 7022subtracts filtered inverted Q output signal 7013 from filtered Q outputsignal 7011, amplifies the result, and outputs Q baseband output signal7086. Because filtered inverted Q output signal 7013 is substantiallyequal to an inverted version of filtered Q output signal 7011, Qbaseband output signal 7086 is substantially equal to filtered Q outputsignal 7013, with its amplitude doubled. Furthermore, filtered Q outputsignal 7011 and filtered inverted Q output signal 7013 may comprisesubstantially equal noise and DC offset contributions of the samepolarity from prior down-conversion circuitry, including third UFDmodule 7010 and fourth UFD module 7014, respectively. When seconddifferential amplifier 7022 subtracts filtered inverted Q output signal7013 from filtered Q output signal 7011, these noise and DC offsetcontributions substantially cancel each other.

Additional embodiments relating to addressing DC offset and re-radiationconcerns, applicable to the present invention, are described inco-pending patent application No., “DC Offset, Re-radiation, and I/QSolutions Using Universal Frequency Translation Technology,” Ser. No.09/526,041, filed on Mar. 14, 2000, now U.S. Pat. No. 6,879,817, whichis herein incorporated by reference in its entirety.

9.1.1 Example I/Q Modulation Control Signal Generator Embodiments

FIG. 70B illustrates an exemplary block diagram for I/Q modulationcontrol signal generator 7023, according to an embodiment of the presentinvention. I/Q modulation control signal generator 7023 generates Icontrol signal 7090, inverted I control signal 7092, Q control signal7094, and inverted Q control signal 7096 used by I/Q modulation receiver7000 of FIGS. 70A1 and 70A2. I control signal 7090 and inverted Icontrol signal 7092 operate to down-convert the I-phase portion of aninput I/Q modulated RF signal. Q

control signal 7094 and inverted Q control signal 7096 act todown-convert the Q-phase portion of the input I/Q modulated RF signal.Furthermore, I/Q modulation control signal generator 7023 has theadvantage of generating control signals in a mariner such that resultingcollective circuit re-radiation is radiated at one or more frequenciesoutside of the frequency range of interest. For instance, potentialcircuit re-radiation is radiated at a frequency substantially greaterthan that of the input RF carrier signal frequency.

I/Q modulation control signal generator 7023 comprises a localoscillator 7025, a first divide-by-two module 7027, a 180 degree phaseshifter 7029, a second divide-by-two module 7031, a first pulsegenerator 7033, a second pulse generator 7035, a third pulse generator7037, and a fourth pulse generator 7039.

Local oscillator 7025 outputs an oscillating signal 7015. FIG. 70C showsan exemplary oscillating signal 7015.

First divide-by-two module 7027 receives oscillating signal 7015,divides oscillating signal 7015 by two, and outputs a half frequency LOsignal 7017 and a half frequency inverted LO signal 7041. FIG. 70C showsan exemplary half frequency LO signal 7017. Half frequency inverted LOsignal 7041 is an inverted version of half frequency LO signal 7017.First divide-by-two module 7027 may be implemented in circuit logic,hardware, software, or any combination thereof, as would be known bypersons skilled in the relevant art(s).

180 degree phase shifter 7029 receives oscillating signal 7015, shiftsthe phase of oscillating signal 7015 by 180 degrees, and outputs phaseshifted LO signal 7019. 180 degree phase shifter 7029 may be implementedin circuit logic, hardware, software, or any combination thereof, aswould be known by persons skilled in the relevant art(s). In alternativeembodiments, other amounts of phase shift may be used.

Second divide-by two module 7031 receives phase shifted LO signal 7019,divides phase shifted LO signal 7019 by two, and outputs a halffrequency phase shifted LO signal 7021 and a half frequency invertedphase shifted LO signal 7043. FIG. 70C shows an exemplary half frequencyphase shifted LO signal 7021. Half frequency inverted phase shifted LOsignal 7043 is an inverted version of half frequency phase shifted LOsignal 7021. Second divide-by-two module 7031 may be implemented incircuit logic, hardware, software, or any combination thereof, as wouldbe known by persons skilled in the relevant art(s).

First pulse generator 7033 receives half frequency LO signal 7017,generates an output pulse whenever a rising edge is received on halffrequency LO signal 7017, and outputs I control signal 7090. FIG. 70Cshows an exemplary I control signal 7090.

Second pulse generator 7035 receives half frequency inverted LO signal7041, generates an output pulse whenever a rising edge is received onhalf frequency inverted LO signal 7041, and outputs inverted I controlsignal 7092. FIG. 70C shows an exemplary inverted I control signal 7092.

Third pulse generator 7037 receives half frequency phase shifted LOsignal 7021, generates an output pulse whenever a rising edge isreceived on half frequency phase shifted LO signal 7021, and outputs Qcontrol signal 7094. FIG. 70C shows an exemplary Q control signal 7094.

Fourth pulse generator 7039 receives half frequency inverted phaseshifted LO signal 7043, generates an output pulse whenever a rising edgeis received on half frequency inverted phase shifted LO signal 7043, andoutputs inverted Q control signal 7096. FIG. 70C shows an exemplaryinverted Q control signal 7096.

In an embodiment, control signals 7090, 7021, 7041 and 7043 includepulses having a width equal to one-half of a period of I/Q modulated RFinput signal 7082. The invention, however, is not limited to these pulsewidths, and control signals 7090, 7021, 7041, and 7043 may comprisepulse widths of any fraction of, or multiple and fraction of, a periodof I/Q modulated RF input signal 7082.

First, second, third, and fourth pulse generators 7033, 7035, 7037, and7039 may be implemented in circuit logic, hardware, software, or anycombination thereof, as would be known by persons skilled in therelevant art(s).

As shown in FIG. 70C, in an embodiment, control signals 7090, 7021,7041, and 7043 comprise pulses that are non-overlapping in otherembodiments the pulses may overlap. Furthermore, in this example, pulsesappear on these signals in the following order: I control signal 7090, Qcontrol signal 7094, inverted I control signal 7092, and inverted Qcontrol signal 7096. Potential circuit re-radiation from I/Q modulationreceiver 7000 may comprise frequency components from a combination ofthese control signals.

For example, FIG. 70D shows an overlay of pulses from I control signal7090, Q control signal 7094, inverted I control signal 7092, andinverted Q control signal 7096.

When pulses from these control signals leak through first, second,third, and/or fourth UFD modules 7002, 7006, 7010, and 7014 to antenna7072 (shown in FIGS. 70A1 and 70A2), they may be radiated from I/Qmodulation receiver 7000, with a combined waveform that appears to havea primary frequency equal to four times the frequency of any single oneof control signals 7090, 7021, 7041, and 7043. FIG. 70 shows an examplecombined control signal 7045.

FIG. 70D also shows an example I/Q modulation RF input signal 7082overlaid upon control signals 7090, 7094, 7092, and 7096. As shown inFIG. 70D, pulses on I control signal 7090 overlay and act todown-convert a positive I-phase portion of I/Q modulation RF inputsignal 7082. Pulses on inverted I control signal 7092 overlay and act todown-convert a negative I-phase portion of I/Q modulation RF inputsignal 7082. Pulses on Q control signal 7094 overlay and act todown-convert a rising Q-phase portion of I/Q modulation RF input signal7082. Pulses on inverted Q control signal 7096 overlay and act todown-convert a falling Q-phase portion of I/Q modulation RF input signal7082.

As FIG. 70D further shows in this example, the frequency ratio betweenthe combination of control signals 7090, 7021, 7041, and 7043 and I/Qmodulation RF input signal 7082 is approximately 4:3. Because thefrequency of the potentially re-radiated signal, i.e., combined controlsignal 7045, is substantially different from that of the signal beingdown-converted, i.e., I/Q modulation RF input signal 7082, it does notinterfere with signal down-conversion as it is out of the frequency bandof interest, and hence may be filtered out. In this manner, I/Qmodulation receiver 7000 reduces problems due to circuit re-radiation.As will be understood by persons skilled in the relevant art(s) from theteachings herein, frequency ratios other than 4:3 may be implemented toachieve similar reduction of problems of circuit re-radiation.

It should be understood that the above control signal generator circuitexample is provided for illustrative purposes only. The invention is notlimited to these embodiments. Alternative embodiments (includingequivalents, extensions, variations, deviations, etc., of theembodiments described herein) for I/Q modulation control signalgenerator 7023 will be apparent to persons skilled in the relevantart(s) from the teachings herein, and are within the scope of thepresent invention.

Additional embodiments relating to addressing DC offset and re-radiationconcerns, applicable to the present invention, are described inco-pending patent application titled “DC Offset, Re-radiation, and I/QSolutions Using Universal Frequency Translation Technology,” which isherein incorporated by reference in its entirety.

9.1.2 Detailed Example I/Q Modulation Receiver Embodiment with ExemplaryWaveforms

FIGS. 70E1 and 70E2 illustrates a more detailed example circuitimplementation of I/Q modulation receiver 7000, according to anembodiment of the present invention. FIGS. 70E-P show example waveformsrelated to an example implementation of I/Q modulation receiver 7000 ofFIGS. 70E1 and 70E2.

FIGS. 70F and 70G show first and second input data signals 7047 and 7049to be I/Q modulated with a RF carrier signal frequency as the I-phaseand Q-phase information signals, respectively.

FIGS. 701 and 70J show the signals of FIGS. 70F and 70G after modulationwith a RF carrier signal frequency, respectively, as I-modulated signal7051 and Q-modulated signal 7053.

FIG. 70H shows an I/Q modulation RF input signal 7082 formed fromI-modulated signal 7051 and Q-modulated signal 7053 of FIGS. 701 and70J, respectively.

FIG. 700 shows an overlaid view of filtered I output signal 7007 andfiltered inverted I output signal 7009.

FIG. 70P shows an overlaid view of filtered Q output signal 7011 andfiltered inverted Q output signal 7013.

FIGS. 70K and 70L show I baseband output signal 7084 and Q basebandoutput signal 7086, respectfully. A data transition 7055 is indicated inboth I baseband output signal 7084 and Q baseband output signal 7086.The corresponding data transition 7055 is indicated in I-modulatedsignal 7051 of FIG. 701, Q-modulated signal 7053 of FIG. 70J, and I/Qmodulation RF input signal 7082 of FIG. 70H.

FIGS. 70M and 70N show I baseband output signal 7084 and Q basebandoutput signal 7086 over a wider time interval.

9.2 Example Single Channel Receiver Embodiment

FIG. 70Q illustrates an example single channel receiver 7091,corresponding to either the I or Q channel of I/Q modulation receiver7000, according to an embodiment of the present invention. Singlechannel receiver 7091 can down-convert an input RF signal 7097 modulatedaccording to AM, PM, FM, and other modulation schemes. Refer to section7.4.1 above for further description on the operation of single channelreceiver 7091.

9.3 Alternative Example I/Q Modulation Receiver Embodiment

FIG. 70R illustrates an exemplary I/Q modulation receiver 7089,according to an embodiment of the present invention. I/Q modulationreceiver 7089 receives, down-converts, and demodulates an I/Q modulatedRF input signal 7082 to an I baseband output signal 7084, and a Qbaseband output signal 7086. I/Q modulation receiver 7089 has additionaladvantages of reducing or eliminating unwanted DC offsets and circuitre-radiation, in a similar fashion to that of I/Q modulation receiver7000 described above.

10. Shunt Transceiver Embodiments Using UFT Modules

In this section, example transceiver embodiments are presented thatutilize UFT modules in a shunt configuration for balanced up-conversionand balanced down-conversion. More specifically, a signal channeltransceiver embodiment is presented that incorporates the balancedtransmitter 5600 (FIG. 56A) and the receiver 7091 (FIG. 70Q).Additionally, an IQ transceiver embodiment is presented that incorporatebalanced IQ transmitter 5700 (FIG. 57) and IQ receiver 7000 (FIGS. 70A1and 70A2).

These transceiver embodiments incorporate the advantages described abovefor the balanced transmitter 5600 and the balanced receiver 7091. Morespecifically, during up-conversion, an input baseband signal isup-converted in a balanced and differential fashion, so as to minimizecarrier insertion and unwanted spectral growth. Additionally, duringdown-conversion, an input RF input signal is down-converted so that DCoffset and re-radiation is reduced or eliminated. Additionally, sinceboth transmitter and receiver utilize UFT modules for frequencytranslation, integration and cost saving can be realized.

These embodiments are described herein for purposes of illustration, andnot limitation. The invention is not limited to these embodiments.Alternate embodiments (including equivalents, extensions, variations,deviations, etc., of the embodiments described herein) will be apparentto persons skilled in the relevant art(s) based on the

teachings contained herein. The invention is intended and adapted toinclude such alternate embodiments.

FIG. 71 illustrates a transceiver 7100 according to embodiments of thepresent invention. Transceiver 7100 includes the single channel receiver7091, the balanced transmitter 5600, a diplexer 7108, and an antenna7112. Transceiver 7100 up-converts a baseband input signal 7110 usingthe balanced transmitter 5600 resulting in an output RF signal 7106 thatis radiated by the antenna 7112. Additionally, the transceiver 7100 alsodown-converts a received RF input signal 7104 using the receiver 7091 tooutput baseband signal 7102. The diplexer 7108 separates the transmitsignal 7106 from the receive signal 7104 so that the same antenna 7112can be used for both transmit and receive operations. The operation oftransmitter 5600 is described above in section 7.1.3, to which thereader is referred for greater detail.

During up-conversion, the transmitter 5600 shunts the input basebandsignal 7110 to ground in a differential and balanced fashion accordingto the control signals 2623 and 2627, resulting in the harmonically richsignal 7114. The harmonically rich signal 7114 includes multipleharmonic images that repeat at harmonics of the sampling frequency ofthe control signals, where each harmonic image contains the necessaryamplitude, frequency, and phase information to reconstruct the basebandsignal 7110. The optional filter 2606 can be included to select adesired harmonic from the harmonically rich signal 7114. The optionalamplifier 2608 can be included to amplify the desired harmonic resultingin the output RF signal 7106, which is transmitted by antenna 7112 afterthe diplexer 7108. A detailed description of the transmitter 5600 isincluded in section 7.1.3, to which the reader is referred for furtherdetails.

During down-conversion, the ‘receiver 7091 alternately shunts thereceived RF signal 7104 to ground according to control signals 7093 and7095, resulting in the down-converted output signal 7102. A detaileddescription of receiver 7091 is included in sections 9.1 and 9.2, towhich the reader is referred for further details.

FIG. 72 illustrates IQ transceiver 7200 according to embodiments of thepresent invention. IQ transceiver 7200 includes the IQ receiver 7000,the IQ transmitter 5700, a diplexer 7214, and an antenna 7216.Transceiver 7200 up-converts an I baseband signal 7206 and a Q basebandsignal 7208 using the IQ transmitter 5700 (FIG. 57) to generate an IQ RFoutput signal 7212. A detailed description of the IQ transmitter 5700 is

included in section 7.2.2, to which the reader is referred for furtherdetails. Additionally, the transceiver 7200 also down-converts areceived RF signal 7210 using the IQ Receiver 7000, resulting in Ibaseband output signal 7202 and a Q baseband output signal 7204. Adetailed description of the IQ receiver 7000 is included in section 9.1,to which the reader is referred for further details.

11. Conclusion

Example implementations of the methods, systems and components of theinvention have been described herein. As noted elsewhere, these exampleimplementations have been described for illustrative purposes only, andare not limiting. Other implementation embodiments are possible andcovered by the invention, such as but not limited to software andsoftware/hardware implementations of the systems and components of theinvention. Such implementation embodiments will be apparent to personsskilled in the relevant art(s) based on the teachings contained herein.

While various application embodiments of the present invention have beendescribed above, it should be understood that they have been presentedby way of example only, and not limitation. Thus, the breadth and scopeof the present invention should not be limited by any of theabove-described exemplary embodiments.

What is claimed is:
 1. An apparatus, comprising: an in-phase channelincluding, a first pair of impedances that receive a first differentialsignal; and a first switch coupled across corresponding outputs of saidfirst pair of impedances, said first switch controlled by a firstcontrol signal having a plurality of pulses; a quadrature channelincluding, a second pair of impedances that receive a seconddifferential signal; and a second switch coupled across correspondingoutputs of said second pair of impedances, said second switch controlledby a second control signal having a plurality of pulses; wherein saidoutputs of said first pair of impedances are wire-ored with said outputsof said second pair of impedances, resulting in an IQ output; andwherein said second control signal is phase-shifted by 270 degrees withrespect to said first control signal.